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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv611/adv612 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 closed circuit tv digital video codec functional block diagram quantizer & entropy coding host i/o port & fifo host adv611/ adv612 256k 3 16-bit dram component video i/o bin width control location, size and contrast control subband statistics 8 16/32 digital video i/o port wavelet filters, decimator & interpolator quality box control on-chip transform buffer dram manager features programmable quality box industrial temperature range (adv612) hardware frame rate reduction 100% bitstream compatible with the adv601 and adv601lc precise compressed bit rate control field independent compression 8-bit video interface supports ccir-656 and multi- plexed philips formats general purpose 16- or 32-bit host interface with 512 deep 32-bit fifo performance real-time compression or decompression of ccir-601 to video: 720 3 288 @ 50 fields/sec pal 720 3 243 @ 60 fields/sec ntsc compression ratios from visually loss-less to 7500:1 visually loss-less compression at 4:1 on natural images (typical) applications cctv cameras and systems time-lapse video tape recorders time-lapse video disk recorders wireless cctv cameras fiber cctv systems general description the adv611/adv612 are low cost, single chip, dedicated func- tion, all-di gital-cmos-vlsi devices capable of supporting visually loss-less to 7500:1 real-time compression and decom- pression of ccir -601 digital video at very high image quality levels. the chips integrate glueless video and host interfaces with on-chip sram to permit low part count, system level implementations suitable for a broad range of applications. the adv611/adv612 are 100% bitstream compatible with the adv601. the adv611/adv612 comes in a 120-lead lqfp package. the adv611/adv612 are video encoders/decoders optimized for closed circuit tv (cctv) applications. with the adv611/ adv612, you can define a portion of each video field to be at a higher quality level relative to the rest of the field. this quality box feature significantly increases compression of less impor- tant background details, while retaining the images overall context. additionally, the unique subband coding architecture of the adv611/adv612 offer many application-specific advantages. a review of the g eneral theory of operation and applying the adv611/adv612 sections will help you get the most use out of the adv 611/adv612 in any given ap plication. the adv611/adv612 accept component digital video through the video interface and outputs a compressed bitstream though the host interface in encode mode. while in decode mode, the adv611/adv612 accept compressed bitstream through the host interface and outputs component digital video through the video interface. the host accesses all of the adv611/adv612s control and status registers using the host interface. figure 2 summarizes the basic function of the part. (continued on page 2) adv7185 decoder adv611/ adv612 adsp-21xx analog video signal image sensor signal or quality box controls from remote site serial or parallel bitstream for transmission or storage digitizer figure 1. typical application
adv611/adv612 C2C rev. 0 table of contents this data sheet gives an overview of the adv611/adv612s functionality and provides details on designing the part into a system. the text of the data sheet is written for an audience with a general k nowledge of designing digital video systems. where appropriate, additional sources of reference material are noted throughout the data sheet. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 comparing the adv6xx family video codecs . . . . . 3 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . 4 general theory of operation . . . . . . . . . . . . . . . . . . 4 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 the wavelet kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 the programmable quantizer . . . . . . . . . . . . . . . . . 8 the run length co der and huf fman coder . . . . . 9 encoding vs. decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 adv611/adv612 register descriptions . . . . . . . . . . 11 video area registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pin function descriptions . . . . . . . . . . . . . . . . . . . . 18 video interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 video formatsCccir-656 . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dram manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 compressed data-stream definition . . . . . . . . . . . . . . . . . . . 24 applying the adv611/adv612 . . . . . . . . . . . . . . . . . . . . 30 using the adv611/adv612 in computer applications . . . . . . 30 using the adv611/adv612 in stand-alone applications . . . . 31 connecting the adv611/adv612 to popular video decoders and encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 getting the most out of adv611/adv612 . . . . . . . 32 how much compression can be expected . . . . . . . . . . . . . . 32 evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 software codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 field rate reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 edge enhancement and detection . . . . . . . . . . . . . . . . . . . . . 32 motion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 adv611/adv612 specifications . . . . . . . . . . . . . . . . . . 33 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 clock signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 ccir-656 video format timing . . . . . . . . . . . . . . . . . . . . . . 35 multiplexed philips video timing . . . . . . . . . . . . . . . . . . . . . 37 host interface (indirect address, indirect register data, and interrupt mask/status) register timing . . . . . . . . . . . 40 host interface (compressed data) register timing . . . . . . . 42 adv611/adv612 lqfp pinouts . . . . . . . . . . . . . . . . . . . . 44 adv611/adv612 pin configuration . . . . . . . . . . . . . . 45 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 general description ( continued from page 1 ) adv611/ adv612 video codec cctv digital video interface host interface digital video in (encode) digital video out (decode) compressed video out (encode) compressed video in (decode) status and control figure 2. functional block diagram the adv611/adv612 adheres to international standard ccir-601 for studio quality digital video. the codec also sup- ports a range of field sizes and rates providing high performance in computer, pal, ntsc, or still image environments. the adv611/adv612 is designed only for real-time interlaced video; full frames of video are formed and processed as two independent fields of data. the adv611/adv612 supports the field rates and sizes in table i. note that the maximum active field size is 720 by 288. the maximum pixel rate is 13.50 mhz. the adv611/adv612 has a generic 16-/32-bit host interface that i ncludes a 512-position, 32-bit wide fifo for compressed video. with additional external hardware, the adv611/adv612s host interface is suitable (when interfaced to other devices) for moving compressed video over pci, isa, scsi, sonet, 10 base t, arcnet, hd sl, adsl and a broad range of digital inter- faces. for a full description of the host interface, see the host interface section. the compressed data rate is determined by the input data rate and the selected compression ratio. the adv611/adv612 can achieve a near constant compressed bit rate by using the current field statistics in the off-chip bin width calculator on the exter- nal dsp or host. the process of calculating bin widths on a dsp or host can be adaptive, optimizing the compressed bit rate in real time. this feature provides a near constant bit rate out of the host interface in spite of scene changes or other types of source material changes that would otherw ise create bit rate burst conditions. for more information on the quantizer, see the programmable quantizer section. the adv611/adv612 typically yields visually loss-less com- pression on natural images at a 4:1 compression ratio. for more information on compression ratios, see the getting the most out of the adv61 1/adv612 section. desired im age quality levels can vary widely in different applications, so it is advisable to evaluate image quality of known source material at different compress ion ratios to find the best compression range for the application. the subband coding architecture of the adv611/ adv612 provides a number of options to stretch compression performance. these options are outlined in the applying the adv611/adv612 section. table i. adv611/adv612 field rates and sizes active active total total standard region region region region field rate pixel rate name horizontal vertical 1 horizontal vertical (hz) (mhz) 2 ccir-601/525 720 243 858 262.5 59.94 13.50 ccir-601/625 720 288 864 312.5 50.00 13.50 notes 1 the maximum active field size is 720 by 288. 2 the maximum pixel rate is 13.5 mhz.
adv611/adv612 C3C rev. 0 the adv611/adv612 are real-time compression integrated circuits designed for remote video surveillance or closed circuit television (cctv) applications. the most important feature of these two devices is the quality box. with this feature the user can define a box of any size and location within each field of video that will be compressed at full contrast while the re- mainder outside the box, or background of the image, is com- pressed at a lower level of contrast. the background contrast level is controlled by the user. the lower the contrast level, the more the image will be compressed. the objective in a given table ii. differences between the adv601, adv601lc, adv611 and adv612 adv601 adv601lc adv611 adv612 bits per component 10 8 8 8 dsp serial port yes no no no package 160 pqfp 120 lqfp 120 lqfp 120 lqfp pin assignments unique unique 98% similar to adv601lc 98% similar to adv601lc temperature range 0 c to +70 c0 c to +70 c0 c to +70 c C25 c to +85 c q ja 31 c/w 35 c/w 35 c/w 35 c/w q jc 7.5 c/w 5 c/w 5 c/w 5 c/w field rate reduction software software hardware hardware stall mode no no yes yes field truncation no no yes yes field size register no no yes yes field bit polarity control no no yes yes evaluation board videolab videopipe cctvpipe cctvpipe target applications professional consumer cctv industrial cctv figure 3. application is to adjust the background contrast to a level that ensures both a recognizable and useful background as well as the highest possible compression. figure 3 shows how this qual- ity box appears in final video. the adv611/adv612 is housed in a plastic lqfp package suitable for cost-sensitive commercial applications. comparing the adv6xx family video codecs the adv6xx video codecs support a range of interface, pack- age, and compression features. table ii compares these codecs: original video image image after compression/decompression shown with different box size and position programmable quality box variable contrast background
adv611/adv612 C4C rev. 0 internal architecture the adv611/adv612 is composed of eight blocks. three of these blocks are interface blocks and five are processing blocks. the interface blocks are the digital video i/o port, the host i/o port and the external dram manager. the processing blocks are the wavelet kernel, the on-chip transform buffer, the programmable quantizer, the run length coder and the huffman coder. digital video i/o port provides a real-time uncompressed video interface to support a broad range of component digital video formats, including d1. host i/o port and fifo carries control, status, and compressed video to and from the host processor. a 512 position by 32-bit fifo buffers the com- pressed video stream between the host and the huffman coder. hardware field rate reduction in cctv applications it is often desirable to reduce the field rate to achieve the highest possible compression. the adv611/ adv612 have special hardware to permit this function. it is possible to set a register on the adv611/adv612 during en- code mode that will automatically reduce the field rate. this is a 5-bit register that allows up to 31 fields to be skipped. stall mode it is possible to stall or halt the adv611/adv612 at any time during encode mode. this allows the user to feed uncompressed video data to these parts and to stop indefinitely between fields or even between pixels. this feature is useful when compressing video that is not coming into the adv611/adv612 at sustained v clk rates. stall mode is enabled by asserting the stall pin at any time during encode. stall mode is enabled on the next clock cycle after the pin is asserted. field size reporting the adv611/adv612 have a read-only register that allows the user to read the field size of the most recently compressed field. this feature is useful in the feedback loop of a precise bit rate controller. the data is valid after lcode (unless an entire compressed field resides in the internal fifo). dram manager performs all tasks related to writing, reading and refreshing the external dram. the external host buffer dram is used for reordering and buffering quantizer input and output values. wavelet kernel (filters, decimator, and interpolator) gathers statistics on a per-field basis and includes a block of filters, interpolators and decimators. the kernel calculates for- ward and backward bi-orthogonal, two-dimensional, separable wavelet transforms on horizontal scanned video data. this block uses the internal transform buffer when performing wavelet transforms calculated on an entire images data and so elimi- nates any need for extremely fast external memories in an adv611/adv612-based design. on-chip transform buffer provides an internal set of sram for use by the wavelet trans- form kernel. its function is to provide enough delay line storage to support calculation of separable two dimensional wavelet transforms for horizontally scanned images. programmable quantizer quantizes wavelet coefficients. quantize controls are calculated by the external dsp or host processor during encode operations and de-quantize controls are extracted from the compressed bitstream during decode. each quantizer bin width is com- puted by the bw calculator software to maintain a constant compressed bit rate or constant quality bit rate. a bin width is a per-block parameter the quantizer uses when determining the number of bits to allocate to each block (subband). quality box the quality box is defined using the video area registers that are described in the registers descriptions section. the back- ground contrast is controlled using background contrast regis- ters that are defined later in this document. it is possible to control both parameters on a per-field basis during encode mode. this enables the quality box to either move slowly across the image or to instantaneously jump from one location to the next. run length coder performs run length coding on zero data and models nonzero data, encoding or decoding for more efficient huffman coding. this data coding is optimized across the subbands and varies depending on the block being coded. huffman coder performs huffman coder and decoder functions on quantized run-length coded coefficient values. the huffman coder/de- coder uses three rom-coded huffman tables that provide ex- cellent performance for wavelet transformed video. field truncation it is possible to set a hard upper limit to the field size of each field during encode mode. the huffman coder is able to de- tect if the field size exceeds a preset threshold and then causes the remaining mallat block data to be zeroed out, therefore, truncating the fields data. the bitstream is truncated in such a way that all end-of-field markers are inserted. this means that the compressed bitstream can still be decompressed by any hardware or software adv6xx decoder. the only penalty is the loss of mallat blocks which, depending on how many are lost, will degrade the image quality of the truncated field. general theory of operation the adv611/adv612 processors compression algorithm is based on the bi-orthogonal (7, 9) wavelet transform, and imple- ments field independent subband coding. subband coders trans- form two-dimensional spatial video data into spatial frequency filtered subbands. the quantization and entropy encoding pro- cesses provide the adv611/adv612s data compression. the wavelet theory, on which the adv611/adv612 is based, is a new mathematical apparatus first explicitly introduced by morlet and grossman in their works on geophysics during the mid 80s. this theory became very popular in theoretical physics and applied math. the late 80s and 90s have seen a dramatic growth in wavelet applications such as signal and image process- ing. for more on wavelet theory by morlet and grossman, see decomposition of hardy functions into square integrable wavelets of constant shape (journal citation listed in references section).
adv611/adv612 C5C rev. 0 block a is high pass in x and decimated by two. block b is high pass in x, high pass in y, and decimated by eight. block c is high pass in x, low pass in y, and decimated by eight. block d is low pass in x, high pass in y, and decimated by eight. block e is high pass in x, high pass in y, and decimated by 32. block f is high pass in x, low pass in y, and decimated by 32. block g is low pass in x, high pass in y, and decimated by 32. block h is high pass in x, high pass in y, and decimated by 128. block i is high pass in x, low pass in y, and decimated by 128. block j is low pass in x, high pass in y, and decimated by 128. block k is high pass in x, high pass in y, and decimated by 512. block l is high pass in x, low pass in y, and decimated by 512. block m is low pass in x, high pass in y, and decimated by 512. block n is low pass in x, low pass in y, and decimated by 512. n m l k i h j g f e c b d a figure 5. modified mallat diagram (block letters correspond to those in filter tree) encode path decode path wavelet kernel filter bank adaptive quantizer run length coder & huffman coder compressed data figure 4. encode and decode paths references for more information on the terms, techniques and underlying principles referred to in this data sheet, you may find the follow- ing reference texts useful. a reference text for general digital video principles is: jack, k., video demystified: a handbook for the digital engineer (high text publications, 1993) isbn 1-878707-09-4 three reference texts for wavelet transform background infor- mation are: vetterli, m., kovacevic, j., wavelets and subband coding (prentice hall, 1995) isbn 0-13-097080-8 benedetto, j., frazier, m., wavelets: mathematics and applica- tions (crc press, 1994) isbn 0-8493-8271-8 grossman, a., morlet, j., decomposition of hardy functions into square integrable wavelets of constant shape , siam. j. math. anal., vol. 15, no. 4, pp 723-736, 1984 the wavelet kernel this block contains a set of filters and decimators that work on the image in both horizontal and vertical directions. figure 8 illustrates the filter tree structure. the filters apply carefully chosen wavelet basis functions that better correlate to the broad- band nature of images than the sinusoidal waves used in dis- crete cosine transform (dct) compression schemes (jpeg, mpeg, and h261). an advantage of wavelet-based compression is that the entire image can be filtered without being broken into sub-blocks as required in dct compression schemes. this full image filtering eliminates the block artifacts seen in dct compression and offers more graceful image degradation at high compression ratios. the availability of full image subband data also makes image processing, scaling, and a number of other system fea- tures possible with little or no computational overhead. the resultant filtered image is made up of components of the original image as is shown in figure 5 (a modified mallat tree). note that figure 5 shows how a component of video would be filtered, but in multiple component video, luminance and color components are filtered separately. in figure 6 and figure 7 an actual image and the mallat tree (luminance only) equivalent is shown. it is important to note that while the image has been filtered or transformed into the frequency domain, no compres- sion has occurred. with the image in its filtered state, it is now ready for processing in the second block, the quantizer. understanding the structure and function of the wavelet filters and resultant product is the key to obtaining the highest perfor- mance from the adv611/adv612. consider the following points: ? the data in all blocks (except n) for all components are high pass filtered. therefore, the mean pixel value in those b locks is typically zero and a histogram of the pixel values in these blocks will contain a single hump (laplacian distribution). ? the data in most blocks is more likely to contain zeros or strings of zeros than unfiltered image data. ? the human visual system is less sensitive to higher frequency blocks than low ones. ? attenuation of the selected blocks in luminance or color com- ponents results in control over sharpness, brightness, contrast and saturation. ? high quality filtered/decimated images can be extracted/created without computational overhead. through leverage of these key points, the adv611/adv612 not only com presses video, but offers a host of application features. please see the applying the adv611/adv612 section for details on getting the most out of the adv611/adv612s subband coding architecture in different applications.
adv611/adv612 C6C rev. 0 figure 6. unfiltered original image (analog devices corporate offices, norwood, massachusetts) figure 7. modified mallat diagram of image
adv611/adv612 C7C rev. 0 low pass in x luminance and color components (each separately) stage 1 indicates decimate by two in x indicates decimate by two in y indicates corresponding block letter on mallat diagram x2 block a y 2 stage 2 stage 3 stage 4 stage 5 high pass in x x2 low pass in x high pass in x x2 x2 low pass in y high pass in y low pass in y high pass in y y 2 y 2 y 2 block b block c block d low pass in x high pass in x x2 x2 low pass in y high pass in y low pass in y high pass in y y 2 y 2 y 2 y 2 block # x2 y2 low pass in x high pass in x block e block f block g x2 x2 low pass in y high pass in y low pass in y high pass in y y 2 y 2 y 2 y 2 low pass in x high pass in x block h block i block j x2 x2 low pass in y high pass in y low pass in y high pass in y y 2 y 2 y 2 y 2 block k block l block m block n figure 8. wavelet filter tree structure
adv611/adv612 C8C rev. 0 41 38 35 32 26 23 29 20 17 14 8 5 11 2 cr component low high quantization of mallat blocks 39 36 33 30 24 21 27 18 15 12 6 3 9 0 y component 40 37 34 31 25 22 28 19 16 13 7 4 10 1 cb component figure 10. typical quantization of mallat data blocks (graphed) the programmable quantizer this block quantizes the filtered image based on the response profile of the human visual system. in general, the human eye cannot resolve high frequencies in images to the same level of accuracy as lower frequencies. through intelligent quantiza- tion of information contained within the filtered image, the adv611/adv612 achieves compression without compromising the visual quality of the image. figure 9 shows the encode and decode data formats used by the quantizer. figure 10 shows how a typical quantization pattern applies over mallat block data. the high frequency blocks receive much larger quantization (appear darker) than the low frequency blocks (appear lighter). looking at this figure, one sees some key point concerning quantization: (1) quantization relates directly to frequency in mallat block data and (2) levels of quantization range widely from high to low frequency block. (note that the fill is based on a log formula.) the relation between actual adv611/adv612 bin width factors and the mallat block fill pattern in figure 10 appears in table iii. 9.7 wavelet data 6.10 1/bw 15.17 data 0.5 15.0 bin number quantizer - encode mode trnc signed signed unsigned 1/bw quantizer - decode mode 8.8 bw 23.8 de-quantized wavelet data 9.7 wavelet data 15.0 bin number signed signed unsigned bw sat figure 9. programmable quantizer data flow
adv611/adv612 C9C rev. 0 table iii. typical quantization of mallat data block data 1 mallat bin width reciprocal bin blocks factors width factors 39 0x007f 0x0810 40 0x009a 0x06a6 41 0x009a 0x06a6 36 0x00be 0x0564 33 0x00be 0x0564 30 0x00e4 0x047e 34 0x00e6 0x0474 35 0x00e6 0x0474 37 0x00e6 0x0474 38 0x00e6 0x0474 31 0x0114 0x03b6 32 0x0114 0x03b6 27 0x0281 0x0199 24 0x0281 0x0199 21 0x0301 0x0155 25 0x0306 0x0153 26 0x0306 0x0153 28 0x0306 0x0153 29 0x0306 0x0153 22 0x03a1 0x011a 23 0x03a1 0x011a 5 0x0a16 0x0066 18 0x0a16 0x0066 12 0x0c1a 0x0055 20 0x0c2e 0x0054 19 0x0c2e 0x0054 17 0x0c2e 0x0054 16 0x0c2e 0x0054 14 0x0e9d 0x0046 13 0x0e9d 0x0046 6 0x1ddc 0x0022 9 0x1ddc 0x0022 3 0x23d5 0x001d 11 0x2410 0x001c 10 0x2410 0x001c 8 0x2410 0x001c 7 0x2410 0x001c 5 0x2b46 0x0018 4 0x2b46 0x0018 0 0xa417 0x0006 2 0xc62b 0x0005 1 0xc62b 0x0005 note 1 the mallat block numbers, bin width factors, and reciprocal bin width factors in table iii correspond to the shading per-cent fill) of mallat blocks in figure 10. the run length coder and huffman coder this block contains two types of entropy coders that achieve mathematically loss-less compression: run-length and huffman. the run-length coder looks for long strings of zeros and replaces them with short hand symbols. table iv illustrates an example of how compression is possible. the huffman coder is a digital compressor/decompressor that can be used for compressing any type of digital data. essentially, an ideal huffman coder creates a table of the most commonly occurring code sequences (typically zero and small values near zero) and then replaces those codes with some shorthand. the adv611/adv612 employs three fixed huffman tables; it does not create tables. the filters and the quantizer increase the number of zeros and strings of zeros, which improves the performance of the entropy coders. the higher the selected compression ratio, the more zeros and small value sequences the quantizer needs to generate. the transformed image in figure 7 shows that the filter bank concentrates zeros and small values in the higher frequency blocks. encoding vs. decoding the decoding of compressed video follows the exact path as encoding but in reverse order. there is no need to calculate bin widths during decode because the bin width is stored in the compressed image during encode. programmers model a host device configures the adv611/adv612 using the host i/o port. the host reads from status registers and writes to control registers through the host i/o port. table v. register description conventions register name register type (indirect or direct, read or write) and address register functional description text bit [#] or bit or bit field name and usage description bit range [high:low] 0 action or indication when bit is cleared (equals 0) 1 action or indication when bit is set (equals 1) table iv. uncompressed versus compressed data using run-length coding 0000000000000000000000000000000000000000000000000000000000000000000(uncompressed) 57 zeros (compressed)
adv611/adv612 C10C rev. 0 0x100 undef 0x101 undef 0x152 undef 0x153 undef 0x80 C 0xa9 undef 0xab undef 0xac undef 0xad undef 0xae undef max luma 0xaa undef 0xb2 undef 0xb1 undef 0xb0 undef 0xaf undef 0xb3 0x0 sum of squares [0 C 41] sum of cb sum of luma sum of cr min luma max cr min cr max cb min cb rbw0 bw0 rbw41 bw41 indirect register address reserved reserved 0x1 0x88 0x7 C 0x7f undef 0x0 0x0980 mode control* 0x2 0x000 hstart 0x3 0x3ff 0x4 0x000 0x5 0x3ff 0x6 undef 0x0 0x4 0x8 0xc byte 3 byte 2 byte 1 undef undef 0x00 undef register address direct (externally accessible) registers indirect (internally indexed) registers {access these registers through the indirect register address and indirect register data registers} *note: you must write 0x0880 to the mode control register on chip reset to select the correct pixel mode byte 0 indirect register data reserved interrupt mask / status reserved compressed data vstart hend vend fifo control reserved reserved reset value 0x8 0xffff compressed field size limit 0x9 0x7 mode control register 2 compressed field size hi 0xb4 0x0 compressed field size lo figure 11. map of adv611/adv612 direct and indirect registers
adv611/adv612 C11C rev. 0 adv611/adv612 register descriptions indirect address register direct (write) register byte offset 0x00. this register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. all indirect write registers are 16 bits wide. the address in this register is auto-incremented on each subsequent access of the in direct data register. this capability enhances i/o performance during modes of operation where the host is calculating bin width contr ols. [15:0] indirect address register, iar[15:0] . holds a 16-bit value (index) that selects the indirect register to read or write through the indirect data register (undefined at reset). [31:16] reserved (undefined read/write zero) indirect register data direct (read/write) register byte offset 0x04 this register holds a 16-bit value read or written from or to the indirect register indexed by the indirect address register. [15:0] i ndirect register data, ird[15:0] . a 16-bit value read or written to the indexed indirect register. undefined at reset. [31:16] reserved (undefined read/write zero) compressed data register direct (read/write) register byte offset 0x08 this register holds a 32-bit sequence from the compressed video bitstream. this register is buffered by a 512 position, 32-bit fifo. for word (16-bit) accesses, ac cess word0 (byte 0 and byte 1) then word1 (byte 2 and byte 3) for correct auto-increment. for a description of the data sequence, see the compressed data stream definition section. [31:0] compressed data register, cdr[31:0] . 32-bit value containing compressed video stream data. at reset, contents undefined. interrupt mask / status register direct (read/write) register byte offset 0x0c this 16-bit register contains interrupt mask and status bits that control the state of the adv611/adv612s hirq pin. with the seven mask bits (ie_lcode, ie_statsr, ie_fifostp, ie_fifosrq, ie_fifoerr, ie_ccirer, ie_merr), select the con- ditions that are ored together to determine the output of the hirq pin. six of the status bits (lcode, statsr, fifostp, merr, fifoerr, ccirer) indicate active interrupt conditions and are sticky bits that stay set until read. because sticky status bits are cleared when read, and these bits are set on the positive edge of the condition coming true, they cannot be read or tested for stable level true conditions multiple times. the fifosrq bit is not sticky. this bit can be polled to monitor for a fifosrq true condition. note: enable this monitoring by using the fifosrq bit and correctly programming dsl and esl fields within the fifo control registers. [0] ccir-656 error in ccir-656 data stream, ccirer . this read only status bit indicates the following: 0 no ccir-656 error condition, reset value 1 unrecoverable error in ccir-656 data stream (missing sync codes) [1] statistics ready, statsr . this read only status bit indicates the following: 0 no statistics ready condition, reset value (stats_r pin lo) 1 statistics ready for bw calculator (stats_r pin hi) [2] last code read, lcode . this read only status bit indicates the last compressed data word for field will be retrieved from the fifo on the next read from the host bus. 0 no last code condition, reset value (lcode pin lo) 1 next read retrieves last word for field in fifo (lcode pin hi) [3] fifo service request, fifosrq . this read only status bit indicates the following: 0 no fifo service request condition, reset value (fifo_srq pin lo) 1 fifo is nearly full (encode) or nearly empty (decode) (fifo_srq pin hi) [4] fifo error, fifoerr . this condition indicates that the host has been unable to keep up with the adv611/adv612s compressed data supply or demand requirements. if this condition occurs during encode, the data stream will not be corrupted until merr indicates that the dram has also overflowed. if this condition occurs during decode, the video output will be corrupted. if the system overflows the fifo (disregarding a fifostp condition) with too many writes in decode mode, fifoerr is asserted. this read only status bit indicates the following: 0 no fifo error condition, reset value (fifo_err pin lo) 1 fifo overflow (encode) or underflow (decode) (fifo_err pin hi)
adv611/adv612 C12C rev. 0 [5] fifo stop, fifostp . this condition indicates that the fifo is full in decode mode and empty in encode mode. in decode mode only, fifostp status actually behaves more conservatively than this. in decode mode, even when fifostp is indicated, there are still 32 empty dwords available in the fifo and 32 more dword writes can safely be performed. this status bit indicates the following: 0 no fifo stop condition, reset value (fifo_stp pin lo) 1 fifo empty (encode) or full (decode) (fifo_stp pin hi) [6] memory error, merr . this condition indicates that an error has occurred at the dram memory interface. this condition can be caused by a defective dram, the inability of the host to keep up with the adv611/adv612 compressed data stream, or bit errors in the data stream. note that the adv611/adv612 recovers from this condition without host intervention. 0 no memory error condition, reset value 1 memory error [7] reserved (always read/write zero) [8] interrupt enable on ccirer, ie_ccirer . this mask bit selects the following: 0 disable ccir-656 data error interrupt, reset value 1 enable interrupt on error in ccir-656 data [9] interrupt enable on statr, ie_statr . this mask bit selects the following: 0 disable statistics ready interrupt, reset value 1 enable interrupt on statistics ready [10] interrupt enable on lcode, ie_lcode . this mask bit selects the following: 0 disable last code read interrupt, reset value 1 enable interrupt on last code read from fifo [11] interrupt enable on fifosrq, ie_fifosrq . this mask bit selects the following: 0 disable fifo service request interrupt, reset value 1 enable interrupt on fifo service request [12] interrupt enable on fifoerr, ie_fifoerr . this mask bit selects the following: 0 disable fifo stop interrupt, reset value 1 enable interrupt on fifo stop [13] interrupt enable on fifostp, ie_fifostp . this mask bit selects the following: 0 disable fifo error interrupt, reset value 1 enable interrupt on fifo error [14] interrupt enable on merr, ie_merr . this mask bit selects the following: 0 disable memory error interrupt, reset value 1 enable interrupt on memory error [15] reserved (always read/write zero) mode control register indirect (read/write) register index 0x00 this register holds configuration data for the adv611/adv612s video interface format and controls several other video interfac e features. for more information on formats and modes, see the video interface section. bits in this register have the following functions: [3:0] video interface format, vif[3:0] . these bits select the interface format. valid settings include the following (all other values are reserved): 0x0 ccir-656, reset value 0x2 mltpx (philips) [4] vclk output divided by two, vclk2 . this bit controls the following: 0 do not divide vclk output (vclko = vclk), reset value 1 divide vclk output by two (vclko = vclk/2) [5] video interface master/slave mode select, m/s . this bit selects the following: 0 slave mode video interface (external control of video timing, hsync-vsync-field are inputs), reset value 1 master mode video interface (adv611/adv612 controls video timing, hsync-vsync are outputs) [6] video interface 525/625 (ntsc/pal) mode select, p/n . this bit selects the following: 0 525 mode video interface, reset value 1 625 mode video interface
adv611/adv612 C13C rev. 0 [7] video interface encode/decode mode select, e/d . this bit selects the following: 0 decode mode video interface (compressed-to-raw) 1 encode mode video interface (raw-to-compressed), reset value [8] reserved (always write zero) [9] video interface bipolar/unipolar color component select, buc . this bit selects the following: 0 bipolar color component mode video interface, reset value 1 unipolar color component mode video interface [10] reserved (always write zero) [11] video interface software reset, swr . this bit has the following effects on adv611/adv612 operations: 0 normal operation 1 software reset. this bit is set on hardware reset and must be cleared before the adv611/adv612 can begin processing. ( reset value ) when this bit is set during encode, the adv611/adv612 completes processing the current field then suspends operation until the swr bit is cleared. when this bit is set during decode, the adv611/adv612 suspends operation immediately and does not resume op eration until the swr bit is cleared. note that this bit must be set whenever any other bit in the mode register is changed. [12] hsync pin polarity, phsync . this bit has the following effects on adv611/adv612 operations: 0 hsync is hi during blanking, reset value 1 hsync is lo during blanking (hi during active) [13] hirq pin polarity, phirq . this bit has the following effects on adv611/adv612 operations: 0 hirq is active lo, reset value 1 hirq is active hi [14] quality box enable, qbe. this bit has the following effect on adv611/adv612 operations: 0 video area registers (hstart, hend, vstart, vend). crop video area, setting cropped area to all 0 quantizations (adv601 mode), reset value 1 video area registers (hstart, hend, vstart, vend). select quality box. quantization of the area outside the box is selected with the background contrast control register. see the video area registers for more information on the quality box. [15] video stall enable, vse. this bit has the following effect on adv611/adv612 operations: 0 video stall disabled (adv601 mode), reset value 1 video stall enabled. fifo control register indirect (read/write) register index 0x01 this register holds the service-request settings for the adv611/adv612s host interface fifo, causing interrupts for the nearl y full and nearly empty levels. because each register is four bits in size, and the fifo is 512 positions, the 4-bit value must be multi plied by 32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). the adv6 11/adv612 uses these settings to determine when to generate a fifo service request related host interrupt (fifosrq bit and fifo_srq pin). [3:0] encode service level, esl[3:0] . the value in this field determines w hen the fifo is considered nearly full on enc ode; a c ondi- tion that generates a fifo service request condition in encode mode. since this register is four bits (16 states), and the fifo is 512 positions, the step size for each bit in this register is 32 positions. the following table summarizes sample states of the register and their meaning. esl interrupt when . . . 0000 disables service requests (fifo_srq never goes hi during encode) 0001 fifo has only 32 positions filled (fifo_srq when >= 32 positions are filled) 1000 fifo is 1/2 full, reset value 1111 fifo has only 32 positions empty (480 positions filled) [7:4] decode service level, dsl[7:4] . the value in this field determines when the fifo is considered nearly empty in decode; a condition that generates a fifo service request in decode mode. because this register is four bits (16 states), and the fifo is 512 positions, the step size for each bit in this register is 32 positions. the following table summarizes sample states of the register and their meaning. dsl interrupt when . . . 0000 disables service requests (fifo_srq never goes hi) 0001 fifo has only 32 positions filled (480 positions empty) 1000 fifo is 1/2 empty, reset value 1111 fifo has only 32 positions empty (fifo_srq when >= 32 positions are empty) [15:8] reserved (always write zero)
adv611/adv612 C14C rev. 0 hstart register indirect (write only) register index 0x02 this register holds the setting for the horizontal start of the adv611/adv612s active video area or quality box. the value in this register is usually set to zero, but in cases where you wish to crop incoming video it is possible to do so by changing hst. [9:0] horizontal start, hst[9:0] . 10-bit value defining the start of the active video region. (0 at reset) [15:10] reserved (always write zero) hend register indirect (write only) register index 0x03 this register holds the setting for the horizontal end of the adv611/adv612s active video area or quality box. if the value is larger than the max size of the selected video mode, the adv611/adv612 uses the max size of the selected mode for hend. [9:0] horizontal end, hen[9:0] . 10-bit value defining the end of the active video region. (0x3ff at reset this value is larger than the max size of the largest video mode) [15:10] reserved (always write zero) vstart register indirect (write only) register index 0x04 this register holds the setting for the vertical start of the adv611/adv612s active video area or quality box. the value in th is register is usually set to zero unless you want to crop the active video. to vertically crop video while encoding, program the vstart and vend registers with actual video line numbers, which differ for each field. the vstart and vend contents must be updated on each field unless the quality box is enabled. perform this updating as part of the field-by-field bw register update process. to perform this dynamic update correctly, the update software must keep track of which field is being processed next. [9:0] vertical start, vst[9:0] . 10-bit value defining the starting line of the active video region, with line numbers from 1-to-625 in pal and 1-to-525 in ntsc. (0 at reset) [15:10] reserved (always write zero) vend register indirect (write only) register index 0x05 this register holds the setting for the vertical end of the adv611/adv612s active video area or quality box. if the value is l arger than the max size of the selected video mode, the adv611/adv612 uses the max size of the selected mode for vend. video area registers when the quality box is disabled (mode control register, bit 14 = 0), the area defined by the hstart, hend, vstart and vend registers is the active area that the wavelet kernel processes. video data outside the active video area is set to minimum lumi- nance and zero chrominance (black) by the adv611/adv612. these registers allow cropping of the input video during compression (encode only), but do not change the image size. figure 12 shows how the video area registers work together. some comments on how these registers work are as follows: ? the vertical numbers include the blanking areas of the video. specifically, a vstart value of 21 will include the first line of active video, and the first pixel in a line corresponds to a value hstart of 0 (for ntsc regular). note that the vertical coordinates start with 1, whereas the horizontal coordinates start with 0. ? the default cropping mode is set for the entire frame. specifi- cally, field 2 starts at a vstart value of 283 (for ntsc regular). when the quality box is enabled (mode control register, bit 14 = 1), the area defined by the hstart, hend, vstart and vend registers is the quality box area, and the rest of the video area is attenuated according to the value in the background contrast control register (indirect register index 0x9). in this mode, the range of values for vstart and vend is 1C243 for ntsc and 1C288 for pal. also note that vstart and vend do not need to be updated for each field in this mode. vstart vend hstart hend zero zero zero x, y active video area 0, 0 zero zero zero zero zero max for selected video mode figure 12. video area and video area registers
adv611/adv612 C15C rev. 0 to vertically crop video while encoding, program the vstart and vend registers with actual video line numbers, which differ for each field. the vstart and vend contents must be updated on each field, unless the quality box is enabled. perform this updating as part of the field-by-field bw register update process. to perform this dynamic update correctly, the update software must keep track of which field is being processed next. [9:0] vertical end, ven[9:0] . 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625 in pal and 1-to-525 in ntsc. (0x3ff at resetthis value is larger than the max size of the largest video mode) [15:10] reserved (always write zero) compressed field size limit indirect (read/write) register index 0x8 [15:0] the dword max count 16 msbs register selects the maximum number of double (32-bit) words for an encoded field. when the value in the dword count registers reaches the dword max count, the quantizer zeroes out all remaining samples in the field. to enable the dword max counts operation, you must set (= 1) bit 4 in indirect register 0x7; all other bits in indirect register 0x7 are reserved ( = 0). note that the 4 lsbs of the max count are 0000, so the max count is selectable in 16-word increments. contains bits [19:4] of the dword max count, reset to 0xffff mode control #2 indirect (read/write) register index 0x9 [2:0] these bits control the contrast/attenuation of the area outside the quality box when the quality box is enabled. the following settings control background contrast. setting contrast/attenuation 000 illegal 001 6 db 010 12 db 011 18 db 100 24 db 101 30 db [3] field polarity bit. this bit reverses the polarity of the field pin. this bit operates as follows: 0 normal field polarity (adv601 mode), reset value 1 reverse field polarity. polarity is opposite to the polarity in the field pin timing diagrams. [8:4] field rate reduction. to reduce this compressed data rate, the adv601 can discard some video fields. set field rate reduction to zero to capture all fields, one to discard every other field, two to discard two fields out of three and so on. maximum possible field rate reduction send only one field out of 32. [9] reserved, must set to 1. this bit must be set to take advantage of merr detection logic. resets to 0. [10] reserved, resets to 1. [11] ignore field bit in decode, setting this bit eliminates black fields if field bits repeat from field to field in decode mod e, resets to 0. sum of squares [0C41] registers indirect (read only) register index 0x080 through 0x0a9 the sum of squares [0C41] registers hold values that correspond to the summation of squared values in corresponding mallat bloc ks [0C41]. these registers let the host or dsp read sum of squares statistics from the adv611/adv612; using these values (with the sum of value, min value, and max value) the host or dsp can then calculate the bw and rbw values. the adv611/adv612 indicates that the sum of squares statistics have been updated by setting (1) the statr bit and asserting the stat_r pin. read the statistics at any time. the host reads these values through the host interface. [15:0] sum of squares, sts[15:0] . 16-bit values [0-41] for corresponding mallat blocks [0-41] (undefined at reset). sum of s quare values are 16-bit codes that represent the most significant bits of values ranging from 40 bits for small blocks to 48 bits for large blocks. the 16-bit codes have the following precision: blocks precision sum of squares precision description 0C2 48.C32 48.-bits wide, left shift code by 32-bits, and zero fill 3C11 46.C30 46.-bits wide, left shift code by 30-bits, and zero fill 12C20 44.C28 44.-bits wide, left shift code by 28-bits, and zero fill 21C29 42.C26 42.-bits wide, left shift code by 26-bits, and zero fill 30C41 40.C24 40.-bits wide, left shift code by 24-bits, and zero fill if the sum of squares code were 0x0 025 for block 10, the actual value would be 0x00 0940000000; if using that same code, 0x0025, for block 30, the actual value would be 0x0025000000. [31:0] reserved (always read zero)
adv611/adv612 C16C rev. 0 sum of luma value register indirect (read only) register index 0x0aa the sum of luma value register lets the host or dsp read the sum of pixel values for the luma component in block 39. the host reads these values through the host interface. [15:0] sum of luma, sl[15:0] . 16-bit component pixel values (undefined at reset) [31:0] reserved (always read zero) sum of cb value register indirect (read only) register index 0x0ab the sum of cb value register lets the host or dsp read the sum of pixel values for the cb component in block 40. the host reads these values through the host interface. [15:0] sum of cb, scb[15:0] . 16-bit component pixel values (undefined at reset) [31:0] reserved (always read zero) sum of cr value register indirect (read only) register index 0x0ac the sum of cr value register lets the host or dsp read the sum of pixel values for the cr component in block 41. the host reads these values through the host interface. [15:0] sum of cr, scr[15:0] . 16-bit component pixel values (undefined at reset) [31:0] reserved (always read zero) min luma value register indirect (read only) register index 0x0ad the min luma value register lets the host or dsp read the minimum pixel value for the luma component in the unprocessed data. the host reads these values through the host interface. [15:0] minimum luma, mnl[15:0] . 16-bit component pixel value (undefined at reset) [31:0] reserved (always read zero) max luma value register indirect (read only) register index 0x0ae the max luma value register lets the host or dsp read the maximum pixel value for the luma component in the unprocessed data. the host reads these values through the host interface. [15:0] maximum luma, mxl[15:0] . 16-bit component pixel value (undefined at reset) [31:0] reserved (always read zero) min cb value register indirect (read only) register index 0x0af the min cb value register lets the host or dsp read the minimum pixel value for the cb component in the unprocessed data. the host reads these values through the host interface. [15:0] minimum cb, mncb[15:0] , 16-bit component pixel value (undefined at reset) [31:0] reserved (always read zero) max cb value register indirect (read only) register index 0x0b0 the max cb value register lets the host or dsp read the maximum pixel value for the cb component in the unprocessed data. the host reads these values through the host interface. [15:0] maximum cb, mxcb[15:0] .16-bit component pixel value (undefined at reset) [31:0] reserved (always read zero)
adv611/adv612 C17C rev. 0 min cr value register indirect (read only) register index 0x0b1 the min cr value register lets the host or dsp read the minimum pixel value for the cr component in the unprocessed data. the host reads these values through the host interface. [15:0] minimum cr, mncr[15:0] . 16-bit component pixel value (undefined at reset) [31:0] reserved (always read zero) max cr value register indirect (read only) register index 0x0b2 the max cr value register lets the host or dsp read the maximum pixel value for the cr component in the unprocessed data. the host reads these values through the host interface. [15:0] maximum cr, mxcr[15:0] . 16-bit component pixel value (undefined at reset) [31:0] reserved (always read zero) compressed field size [hi] indirect (read only) register index 0x83 [15:0] the dword count registers hold the count of double (32-bit) words contained in the previously encoded field. this count is useful for bit rate control algorithms that use a servo loop, which is locked to the expected number of double words in the field. the registers are double buffered to ensure that the count remains constant while the next field's count accumu- lates. contains bits [19:4] of the dword count, reset is 0. compressed field size [lo] indirect (read only) register index 0xb4 [3:0] contains bits [3:0] of the dword count, reset is 0. for more information, see the dword count 16 msb register description. bin width and reciprocal bin width registers indirect (read/write) register index 0x0100-0x0153 the rbw and bw values are calculated by the host or dsp from data in the sum of squares [0-41], sum of value, min v alue, and max value registers; then are written to rbw and bw registers during encode mode to control the quantizer. the host writes thes e values through the host interface. these registers contain a 16-bit interleaved table of alternating rbw/bw (rbw-even addresses and bw-odd addresses) values as indexed on writes by address register. bin widths are 8.8, unsigned, 16-bit, fixed-point values. reciprocal bin widths are 6.10 , un- signed, 16-bit, fixed-point values. operation of this register is controlled by the host driver or the dsp (84 total entries) ( undefined at reset). [15:0] bin width values, bw[15:0] [15:0] reciprocal bin width values, rbw[15:0]
adv611/adv612 C18C rev. 0 pin function descriptions clock pins name pins i/o description vclk/xtal 2 i a single clock (vclk) or crystal input (across vclk and xtal). an acceptable 50% duty cycle clock signal is 27 mhz (ccir-601 ntsc/pal). if using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. if using a clock input, use a ttl level input, 50% duty cycle clock with 1 ns (or less) jitter (measured rising edge to rising edge). slowly varying, low jitter clocks are acceptable; up to 5% frequency variation in 0.5 sec. vclko 1 o vclk output or vclk output divided by two. select function using mode control register. video interface pins name pins i/o description vsync 1 i or o vertical sync or vertical blank. this pin can be either an output (master mode) or an input (slave mode). the pin operates as follows: ? output (master) hi during inactive lines of video and lo otherwise ? input (slave) a hi on this input indicates inactive lines of video hsync 1 i or o horizontal sync or horizontal blank. this pin can be either an output (master mode) or an input (slave mode). the pin operates as follows: ? output (master) hi during inactive portion of video line and lo otherwise ? input (slave) a hi on this input indicates inactive portion of video line note that the polarity of this signal is modified using the mode control register. for detailed timing information, see the video interface section. field 1 i or o field # or frame sync. polarity of field pin can be reversed by setting bit 3 in mode control register 2. the pin operates as follows: ? output (master) hi during field1 lines of video and lo otherwise ? input (slave) a hi on this input indicates field1 lines of video enc 1 o encode or decode. this output pin indicates the coding mode of the adv611/ adv612 and operates as follows: ? lo decode mode (video interface is output) ? hi encode mode (video interface is input) note that this pin can be used to control bus enable pins for devices connected to the adv611/adv612 video interface. vdata[7:0] 8 i/o 4:2:2 video data (8-bit digital component video data). these pins are inputs during encode mode and outputs during decode mode. when outputs (decode) these pins are compatible with 50 pf loads (rather than 30 pf as all other busses) to meet the high performance and large number of typical loads on this bus. the performance of these pins varies with the video interface mode set in the mode control register, see the video interface section of this data sheet for pin assignments in each mode. note that the mode control register also sets whether the color component is treated as either signed or unsigned. stall 1 i stall mode. this pin stalls incoming video data driving encode.
adv611/adv612 C19C rev. 0 dram interface pins name pins i/o description ddat[15:0] 16 i/o dram data bus. the adv611/adv612 uses these pins for 16-bit data read/ write operations to the external 256k 16-bit dram. (the operation of the dram interface is fully automatic and controlled by internal functionality of the adv611/adv612.) these pins are compatible with 30 pf loads. dadr[8:0] 9 o dram address bus. the adv611/adv612 uses these pins to form the multi- plexed row/column address lines to the external dram. (the operation of the dram interface is fully automatic and controlled by internal functionality of the adv611/adv612.) these pins are compatible with 30 pf loads. ras 1 o dram row address strobe. this pin is compatible with 30 pf loads. cas 1 o dram column address strobe. this pin is compatible with 30 pf loads. we 1 o dram write enable. this pin is compatible with 30 pf loads. note that the adv611/ adv612 does not have a dram oe pin. tie the drams oe pin to ground. host interface pins name pins i/o description data[31:0] 32 i/o host data bus. these pins make up a 32-bit wide host data bus. the host controls this asynchronous bus with the wr , rd , be and cs pins to commu- nicate with the adv611/adv612. these pins are compatible with 30 pf loads. adr[1:0] 2 i host dword address bus. these two address pins let you address the adv611/adv612s four directly addressable host interface registers. for an illustration of how this addressing works, see the control and write register map figure and status and read register map figure. the adr bits permit register addressing as follows: adr1 adr0 dword address byte address 0 0 0 0x00 0 1 1 0x04 1 0 2 0x08 1 1 3 0x0c be0 C be1 2 i host word enable pins. these two input pins select the words that the adv611/ be2 C be3 adv612s direct and indirect registers access through the host interface; be0 C be1 access the least significant word, and be2 C be3 access the most significant word. for a 32-bit interface only, tie these pins to ground, making all words available. some important notes for 16-bit interfaces are as follows: ? when using these byte enable pins, the byte order is always the lowest byte ? to the higher bytes. ? the adv611/adv612 advances to the next 32-bit com pressed data fifo ? location a fter the be2 C be3 pin is asserted then de-asserted (when accessing the ? compressed data register); so the fifo location only advances when and if ? the host reads or writes the msw of a fifo loca tion. ? the adv611/adv612 advances to the next 16-bit ind irect register after the ? be0 C be1 pin is asserted then de-asserted; so the register selection only advances ? when and if the host reads or writes the msw of a 16-bit indirect register. cs 1 i host chip select. this pin operates as follows: ? lo qualifies host interface control signals ? hi three-states data[31:0] pins wr 1 i host write. host register writes occur on the rising edge of this signal. rd 1 i host read. host register reads occur on the low true level of this signal.
adv611/adv612 C20C rev. 0 host interface pins ( continued ) name pins i/o description ack 1 o host acknowledge. the adv611/adv612 acknowledges completion of a host interface access by asserting this pin. most host interface accesses (other than the compressed data register access) result in ack being held high for at least one wait cycle, but some exceptions to that rule are as follows: ? a full fifo during decode operations causes the adv 611/adv612 to de-assert ? (drive hi) the ack pin, holding off further writes of compressed data until ? the fifo has one available location. ? an empty fifo during encode operations causes the adv611/adv612 to de- ? assert (drive hi) the ack pin, holding off further reads until one location is filled. fifo_srq 1 o fifo service request. this pin is an active high signal indicating that the fifo needs to be serviced by the host. (see fifo control register). the state of this pin also appears in the interrupt mask/status register. use the interrupt m ask to assert a host interrupt ( hirq pin) based on the state of the fifo_srq pin. t his pin oper- ates as follows: ? lo no fifo service request condition (fifosrq bit lo) ? hi fifo needs service is nearly full (encode) or nearly empty (decode) during encode, fifo_srq is lo when the swr bit is cleared (0) and goes hi when the fifo is nearly full (see fifo control register). during decode, fifo_srq is hi when the swr bit is cleared (0), because fifo is empty, and goes lo when the fifo is filled beyond the nearly empty condition (see fifo control register). stats_r 1 o statistics ready. this pin indicates the wavelet statistics (contents of sum of squares, sum of value, min value, max value registers) have been updated and are ready for the bin width calculator to read them from the host in terface. the frequency of this interrupt will be equal to the field rate. the state of this pin also appears in the interrupt mask/status register. use the interrupt mask to assert a host interrupt ( hirq pin) based on the state of the stats_r pin. this pin oper- ates as follows: ? lo no statistics ready condition (statsr bit lo) ? hi statistics ready for bw calculator (statsr bit hi) lcode 1 o last compressed data (for field). this bit indicates the last compressed data word for field will be retrieved from the fifo on the next read from the host bus. the frequency of this interrupt is similar to the field rate, but varies depending on compression and host response. the state of this pin also appears in the interrupt mask/status register. use the interrupt mask to assert a host interrupt ( hirq pin) based on the state of the lcode pin. this pin operates as follows: ? lo no last code condition (lcode bit lo) ? hi last data word for field has been read from fifo (lcode bit hi) hirq 1 o host interrupt request. this pin indicates an interrupt request to the host. the interrupt mask/status register can select conditions for this interrupt based on any or all of the following: fifostp, fifosrq, fifoerr, lcode, statr or ccir-656 unrecoverable error. note that the polarity of the hirq pin can be modified using the mode control register. reset 1 i adv611/adv612 chip reset. asserting this pin returns all registers to reset state. note that the adv611/adv612 must be reset at least once after power-up with this active low signal input. for more information on reset, see the swr bit description. power supply pins name pins i/o description gnd 16 i ground vdd 13 i +5 v dc digital power
adv611/adv612 C21C rev. 0 video interface the adv611/adv612 video interface supports two types of component digital video (d1) interfaces in both compression (input) and decompression (output) modes. these digital video interfaces include support for the multiplexed philips 4:2:2 and ccir-656/smpte125minternational standard. video interface master and slave modes allow for the generation or receiving of synchronization and blanking signals. definitions for the different formats can be found later in this section. for recom- mended connections to popular video decoders and encoders, see the connecting the adv611/adv612 to popular video decoders and encoders section. a complete list of supported video interfaces and sampling rates is included in table vi. table vi. component digital video interfaces nominal bits/ color date name component space sampling rate (mhz) i/f width ccir-656 8 ycrcb 4:2:2 27 8 multiplex philips 8 yuv 4:2:2 27 8 internally, the video interface translates all video formats to one consistent format to be passed to the wavelet kernel. this con- sistent internal video standard is 4:2:2 at 16 bits accuracy. vitc and closed captioning support the video interface also supports the direct loss-less extraction of 90-bit vitc codes during encode and the insertion of vitc codes during decode. closed captioning data (found on active video line 21) is handled just as normal active video on an active scan line. as a result, no special dedicated support is necessary for closed captioning. the data rates for closed captioning data are low enough to ensure robust operation of this mechanism at compression ratios of 50:1 and higher. note that you must include video line 21 in the adv611/adv612s defined active video area for closed caption support. 27 mhz nominal sampling there is one clock input (vclk) to support all internal process- ing elements. this is a 50% duty cycle signal and must be syn- chronous to the video data. internally this clock is doubled using a phase locked loop to provide for a 54 mhz internal processing clock. the clock interface is a two pin interface that allows a crystal oscillator to be tied across the pins or a clock oscillator to drive one pin. the nominal clock rate for the video interface is 27 mhz. note that the adv611/adv612 also supports a pixel rate of 13.5 mhz. video interface and modes in all, there are seven programmable features that configure the video interface. these are: ? encode-decode control in addition to determining what functions the internal pro- cessing elements must perform, this control determines the direction of the video interface. in decode mode, the video interface outputs data. in encode mode, the interface receives data. the state of the control is reflected on the enc pin. this pin can be used as an enable input by external line driv- ers. this control is maintained by the host processor. ? master-slave control this control determines whether the adv611/adv612 gen- erates or receives the vsync, hsync, and field signals. in master mode, the adv611/adv612 generates these sig- nals for external hardware synchronization. in slave mode, the adv611/adv612 receives these signals. note that some video formats require the adv611/ adv612 to operate in slave mode only. this control is maintained by the host processor. ? 525-625 (ntsc-pal) control this control determines whether the adv611/adv612 is operating on 525/ntsc video or 625/pal video. this infor- mation is used when the adv611/adv612 is in master and decode modes so that the adv611/adv612 knows where and when to generate the hsync, vsync, and field pulses as well as when to insert the sav and eav time codes (for ccir-656 only) in the data stream. this control is main- tained by the host processor. table vii shows how the 525- 625 control in the mode control register works. table vii. square pixel control, 525-625 control, and video formats max max 525-625 horizontal field control size size ntsc-pal 0 720 243 ccir-601 ntsc 1 720 288 ccir-601 pal ? bipolar/unipolar color component this mode determines whether offsets are used on color com- ponents. in philips mode, this control is usually set to bipo- lar, since the color components are normal twos-compliment signed values. in ccir-656 mode, this control is set to uni- polar, since the color components are offset by 128. note that it is likely the adv611/adv612 will function if this control is in the wrong state, but compression performance will be degraded. it is important to set this bit correctly. ? active area control four registers hstart (horizontal start), hend (horizon- tal end), vstart (vertical start) and vend (vertical end) determine the active video area. the maximum active video area is 720 by 288 pixels for a single field. ? video format this control determines the video format that is supported. in general, the goal of the various video formats is to support glueless interfaces to the wide variety of video formats periph- eral components expect. this control is maintained by the host processor. table viii shows a synopsis of the supported video formats. definitions of each format can be found later in this section. for video interface pins descriptions, see the pin function descriptions.
adv611/adv612 C22C rev. 0 table ix. ccir-656 master and slave modes hsync, vsync, and field functionality hsync, vsync and field master mode (hsync, vsync slave mode (hsync, vsync functionality for ccir-656 and field are outputs) and field are inputs) encode mode (video data is input pins are driven to reflect the states of the these pins are used to control the to the chip) received time codes: eav and sav. this blanking of video and sequencing (used functionality is independent of the state of with video decoders that do not con- the 525-625 mode control. an encoder is form to the correct number of samples most likely to be in master mode. per line [e.g., the harris 8115]). decode mode (video data is output pins are output to the precise timing definitions undefineduse master mode from the chip) for ccir-656 interfaces. the state of the pins reflect the state of the eav and sav timing codes that are generated in the output video data. these definitions are different for 525 and 625 line systems. the adv611/adv612 completely manages the generation and timing of these pins. clocks and strobes all video data is synchronous to the video clock (vclk). the rising edge of vclk is used to clock all data into the adv611/adv612. synchronization and blanking pins three signals, which can be configured as inputs or outputs, are used for video frame and field horizontal synchronization and blanking. these signals are vsync, hsync, and field. vdata pins functions with differing video interface formats the functionality of the video interface pins depends on the current video format. video formatsccir-656 the adv611/adv612 supports a glueless video interface to ccir-656 devices w hen the video format is programmed to ccir-656 mode. ccir-656 requires that 4:2:2 data (8 bits per component) be multiplexed and transmitted over a single 8-bit physical interface. a 27 mhz clock is transmitted along with the data. this clock is synchronous with the data. the color space of ccir-656 is ycrcb. when in master mode, the ccir-656 mode does not require any external synchronization or blanking signals to accompany digital video. instead, ccir-656 includes special time codes in the stream syntax that define horizontal blanking periods, table viii. component digital video formats nominal bit/ color data rate master/ format name component space sampling (mhz) slave i/f width number ccir-656 8 ycrcb 4:2:2 27 master 8 0x0 multiplex philips 8 yuv 4:2:2 27 either 8 0x2 vertical blanking periods, and field synchronization (horizontal and vertical synchronization information can be derived). these time codes are called end-of-active-video (eav) and start-of- active-video (sav). each line of video has one eav and one sav time code. eav and sav have three bits of embedded information to define hsync, vsync and field information as well as error detection and correction bits. vclk is driven with a 27 mhz, 50% duty cycle clock which is synchronous with the video data. video data is clocked on the rising edge of the vclk signal. when decoding, the vclk signal is typically transmitted along with video data in the ccir-656 physical interface. electrically, ccir-656 specifies differential ecl levels to be used for all interfaces. the adv611/adv612, however, only supports unipolar, ttl logic thresholds. systems designs that interface to strictly conforming ccir-656 devices (especially when interf acing over long cable distances) must include ecl level shifters and line drivers. the functionality of hsync, vsync and field pins is dependent on three programmable modes of the adv611/ adv612: master-slave control, encode-decode control and 525-625 control. table x summarizes the functionality of these pins in various modes.
adv611/adv612 C23C rev. 0 video formatsreferences for more information on video interface standards, see the following reference texts. ? for the definition of ccir-601: 1992 C ccir recommendations rbt series broadcasting service (television) rec. 601-3 encoding parameters of digital television for studios , page 35, september 15, 1992. ? for the definition of ccir-656: 1992 C ccir recommendations rbt series broadcasting service (television) rec. 656-1 interfaces for digital component video signals in 525 and 626 line television systems operating at the 4:2:2 level of rec. 601 , page 46, september 15, 1992. host interface the adv611/adv612 host interface is a high performance interface that passes all command and real-time compressed video data between the host and codec. a 512 position by 32-bit wide, bidirectional fifo buffer passes compressed video data to and from the host. the host interface is capable of burst transfer rates of up to 132 million bytes per second (4 33 mhz). for host interface pins descriptions, see the pin function de- scriptions section. for host interface timing information, see the host interface timing section. video formats multiplexed philips video the adv611/adv612 supports a hybrid mode of operation that is a cross between standard dual lane philips and single lane ccir-656. in this mode, video data is multiplexed in the same fashion in ccir-656, but the values 0 and 255 are not reserved as signaling values. inst ead, external hsync and vsync pins are used for signal ing and video synchronization. vclk may range up to 27 mhz. vclk is driven with up to a 27 mhz 50% duty cycle clock synchronous with the video data. video data is clocked on the rising edge of the vclk signal. the functionality of hsync, vsync, and field pins is dependent on three programmable modes of the adv611/adv612; master-slave control, encode- decode control, and 525-625 control. table ix summarizes the functionality of these pins in various modes. table x. philips multiplexed video master and slave modes hsync, vsync, and field functionality hsync, vsync and field functionality for multiplexed master mode (hsync, vsync slave mode (hsync, vsync philips and field are outputs) and field are inputs) encode mode (video data is input the adv611/adv612 completely manages the generation these pins are used to control the to the chip) and timingof these pins. the device driving the adv611/ blanking of video and sequencing. adv612 video interface must use these outputs to remain in sync with the adv611/adv612. it is expected that this combination of modes would not be used freque ntly. decode mode (video data is output the adv611/adv612 completely manages the generation these pins are used to control the from the chip) and timing of these pins. blanking of video and sequencing. dram manager the dram manager provides a sorting and reordering func- tion on the subband coded data between the wavelet kernel and the programmable quantizer. the dram manager pro- vides a pipeline delay stage to the adv611/adv612. this pipeline lets the adv611/adv612 extract current field image statistics (min/max pixel values, sum of pixel values, and sum of squares) used in the calculation of bin widths and reorder wavelet transform data. the use of current field statistics in the bin width calculation results in precise control over the com- pressed bit rate. the dram manager manages the entire opera- tion and refresh of the dram. the interface between the adv611/adv612 dram man- ager and d ram is designed to be transparent to the user. the adv611/adv612 dram pins should be connected to the dram as called out in the pin function descriptions section. the adv611/adv612 requires one 256k word by 16-bit, 60 ns dram. the following is a selected list of manufacturers and part numbers. all parts can be used with the adv611/ adv612 at all vclk. any dram used with the adv611/ adv612 must meet the minimum specifications outlined for the hyper mode drams listed in table xi. for dram inter- face pins descriptions, see the pin function descriptions. table xi. compatible drams manufacturer part number notes toshiba tc514265dj/dz/dft-60 none nec m pd424210ale-60 none nec m pd42s4210ale-60 cbr self-refresh feature of this product is not needed by the adv611/adv612. hitachi hm514265cj-60 none
adv611/adv612 C24C rev. 0 (continuous stream of frames) time frame (n) frame (n + 1) frame (n + 2) frame (n + m) field 2 sequence field 1 sequence field sequence structure first block sequence complete block sequence vertical interface time code first block sequence structure data for mallat block 6 bin width quantizer code sub-band type code complete block sequence order (stream of mallat block sequences) sequence for mallat block 3 sequence for mallat block 20 sequence for mallat block 9 complete block (individual) sequence structure data for mallat block bin width quantizer code start of block code start of field 1 or 2 code figure 13. hierarchical structure of wavelet compressed frame data (data block order) compressed data-stream definition through its host interface the adv611/adv612 outputs (dur- ing encode) and receives (during decode) compressed digital video data. this stream of data passing between the adv611/ adv612 and the host is hierarchically structured and broken up into blocks of data as shown in figure 13. table v shows pseudo code for a video data transfer that matches the transfer order shown in figure 13 and uses the code names shown in table xiv. the blocks of data listed in figure 13 correspond to wavelet compressed s ections of each field illustrated in figure 13 as a modified mallat diagram.
adv611/adv612 C25C rev. 0 table xii. pseudo-code describing a sequence of video fields complete sequence: frame n; field 1 frame n; field 2 frame n+1; field 1 frame n+1; field 2 (field sequences) frame n+m; field 1 frame n+m; field 2 #eos required in decode to let the adv611/adv612 know the sequence of fields is complete. field 1 sequence: #sof1 field 2 sequence: #sof2 first block sequence: complete block sequence: ... (block sequences) ... block sequence: #sob1, #sob2, #sob3, #sob4 or #sob5
adv611/adv612 C26C rev. 0 6 3 0 39 36 33 30 24 21 27 18 15 12 9 y component 40 37 34 31 25 22 28 19 16 13 7 4 10 1 cb component 26 23 29 20 17 14 8 5 11 2 41 38 35 32 cr component figure 14. block order of wavelet compressed field data (modified mallat diagram) in general, a frame of data is made up of odd and even fields as shown in figure 13. each field sequence is made up of a first block sequence and a complete block sequence. the first block sequence is separate from the complete block se- quence. the complete block sequence contains the remaining 41 block sequences (see block numbering in figure 14). each block sequence contains a start of block delimiter, bin width for the block and actual encoder data for the block. a pseudo code bitstream example for one complete field of video is shown in table xiii. a pseudo code bitstream example for one sequence of fields is shown in table xiv. an example listing of a field of video in adv611/adv612 bitstream format appears in table xvii.
adv611/adv612 C27C rev. 0 table xiii. pseudo code of compressed video data bitstream for one field of video block sequence data for mallat block number . . . #sofn n indicates field 1 or 2 huff_data indicates mallat block 6 data a typical bin width (bw) factor for this block is 0x1ddc #sob4 mallat block 9 datatypical bw = 0x1ddc #sob3 mallat block 20 datatypical bw = 0x0c2e #sob3 mallat block 22 datatypical bw = 0x03a1 #sob3 mallat block 19 datatypical bw = 0x0c2e #sob3 mallat block 23 datatypical bw = 0x03a1 #sob3 mallat block 17 datatypical bw = 0x0c2e #sob3 mallat block 25 datatypical bw = 0x0306 #sob3 mallat block 16 datatypical bw = 0x0c2e #sob3 mallat block 26 datatypical bw = 0x0306 #sob3 mallat block 14 datatypical bw = 0x0e9d #sob3 mallat block 28 datatypical bw = 0x0306 #sob3 mallat block 13 datatypical bw = 0x0e9d #sob3 mallat block 29 datatypical bw = 0x0306 #sob3 mallat block 11 datatypical bw = 0x2410 #sob1 mallat block 31 datatypical bw = 0x0114 #sob3 mallat block 10 datatypical bw = 0x2410 #sob1 mallat block 32 datatypical bw = 0x0114 #sob3 mallat block 8 datatypical bw = 0x2410 #sob1 mallat block 34 datatypical bw = 0x00e5 #sob3 mallat block 7 datatypical bw = 0x2410 #sob1 mallat block 35 datatypical bw = 0x00e6 #sob3 mallat block 5 datatypical bw = 0x2b46 #sob1 mallat block 37 datatypical bw = 0x00e6 #sob3 mallat block 4 datatypical bw = 0x2b46 #sob1 mallat block 38 datatypical bw = 0x00e6 #sob3 mallat block 2 datatypical bw = 0xc62b #sob1 mallat block 40 datatypical bw = 0x009a #sob3 mallat block 1 datatypical bw = 0xc62b #sob1 mallat block 41 datatypical bw = 0x009a #sob4 mallat block 0 datatypical bw = 0xa417 #sob2 mallat block 39 datatypical bw = 0x007f #sob4 mallat block 12 datatypical bw = 0x0c1a #sob2 mallat block 36 datatypical bw = 0x00be #sob4 mallat block 15 datatypical bw = 0x0a16 #sob2 mallat block 33 datatypical bw = 0x00be #sob4 mallat block 18 datatypical bw = 0x0a16 #sob2 mallat block 30 datatypical bw = 0x00e4 #sob2 mallat block 21 datatypical bw = 0x0301 #sob2 mallat block 27 datatypical bw = 0x0281 #sob2 mallat block 24 datatypical bw = 0x0281 #sob4 mallat block 3 datatypical bw = 0x23d5 table xiv specifies the mallat block transfer order and associated start of block (sob) codes. any of these sob codes can be replaced with an sob#5 code for a zero data block. table xiv. pseudo code of compressed video data bitstream for one sequence of video fields block sequence data for mallat block number #sof1 /* mallat block 6 data */ ... (41 #sobn blocks) #sof2 /* mallat block 6 data */ ... (41 #sobn blocks) . (any number of fields in sequence) #eos /* required in decode to end field sequence*/
adv611/adv612 C28C rev. 0 table xv. adv611/adv612 field and block delimiters (codes) code name code description (align all #delimiter codes to 32-bit boundaries) #sof1 0xffffffff40000000 start of field delimiter identifies field1 data. #sof1 resets the huffman decoder and is sufficient on its own to reset the processing of the chip during decode. please note that this code or #sof2 are the only delimiters necessary between adjacent fields. #sof1 operates identically to #sof2 except that during decode it can be used to differentiate between field1 and field2 in the generation of the field signal (master mode) and/or sav/eav codes for ccir-656 modes. #sof2 0xffffffff41000000 start of field delimiter identifies field2 data. #sof resets the huffman decoder and is sufficient on its own to reset the processing of the chip during decode. please note that this code or #sof1 are the only delimiters necessary between adjacent fields. #sof2 operates identically to #sof1 except that during decode it can be used to differentiate between field2 and field1 in the generation of the field signal (master mode) and/or sav/eav codes for ccir-656 modes. (96 bits) this is a 12-byte string of data extracted by the video interface during encode operations and inserted by the video interface into the video data during decode operations. the data content is 90 bits in length. for a complete description of vitc format, see pages 175-178 of video demystified: a handbook for the digital engineer (listed in references section). 0x81 this is an 8-bit delimiter-less type code for the first subband block of wavelet data. (model 1 chroma) 0x82 this is an 8-bit delimiter-less type code for the first subband block of wavelet data. (model 1 luma) 0x83 this is an 8-bit delimiter-less type code for the first subband block of wavelet data. (model 2 chroma) 0x84 this is an 8-bit delimiter-less type code for the first subband block of wavelet data. (model 2 luma) #sob1 0xffffffff81 start of block delimiter identifies the start of huffman coded subband data. this #sob2 0xffffffff82 delimiter will reset the huffman decoder if a system ever experiences bit errors or gets #sob3 0xffffffff83 out of sync. the order of blocks in the frame is fixed and therefore implied in the bit #sob4 0xffffffff84 stream and no unique #sob delimiters are needed per block. there are 41 #sob #sob5 0xffffffff8f delimiters and associated bw and huffman data within a field. #sob1 is differenti ated from #sob2, #sob3 and #sob4 in that they indicate which model and huffman table was used in the run length coder for the particular block: #sob1 model 1 chroma #sob2 model 1 luma #sob3 model 2 chroma #sob4 model 2 luma #sob5 zero data block. all data after this delimiter and before the next start of block delimiter is ignored (if present at all) and assumed zero including the bw value. (16 bits, 8.8) this data code is not entropy coded, is always 16 bits in length and defines the bin width quantizer control used on all data in the block subband. during decode, this value is used by the quantizer. if this value is set to zero during decode, all huffman data is presumed to be zero and is ignored, but must be included. during encode, this value is calculated by the external host and is inserted into the bitstream by the adv611/adv612 (this value is not used by the quantizer). another value calculated by the host, 1/bw is actually used by the quantizer during encode. (modulo 32) this data is the quantized and entropy coded block subband data. the datas length is dependent on block size and entropy coding so it is therefore variable in length. this field is filled with 1s making it modulo 32 bits in length. any huffman decode process can be interrupted and reset by any unexpectedly received # delimiter following a bit error or synchronization problem. #eos 0xffffffffc0ffffff the host sends the #eos (end of sequence) to the adv611/adv612 during decode after the last field in a sequence to indicate that the field sequence is complete. the adv611/ adv612 does not append this code to the end of encoded field sequences; it must be added by the host.
adv611/adv612 C29C rev. 0 table xvi. video data bitstream for one field in a video sequence 1 ffff ffff 40 00 0000 0000 0000 0000 0000 0000 0000 8400 00ff df0d 8eff ffff ffff 84 00 00ff df0c daff ffff ffff 83 00 00ff 609f ffff ffff ffff 83 00 00fe c5af ffff ffff ffff 83 00 00ff 609f ffff ffff ffff 83 00 00fe c5af ffff ffff ffff 83 00 00ff 609f ffff ffff ffff 83 00 00fe c70f ffff ffff ffff 83 00 00ff 609f ffff ffff ffff 83 00 00fe c70f ffff ffff ffff 83 00 00ff 609f ffff ffff ffff 83 00 00fe c78f ffff ffff ffff 83 00 00ff 609f ffff ffff ffff 83 00 00fe c78f ffff ffff ffff 83 00 00ff 6894 3fff ffff ffff 81 1d 40f0 90ff ffff ffff ffff 83 00 00ff 6894 3fff ffff ffff 81 1d 40f0 90ff ffff ffff ffff 83 00 00ff 68aa bfff ffff ffff 81 16 80f0 9bff ffff ffff ffff 83 00 00ff 68aa bfff ffff ffff 81 16 80f0 9bff ffff ffff ffff 83 00 00ff 6894 3fff ffff ffff 81 16 80f0 9fff ffff ffff ffff 83 00 00ff 6894 3fff ffff ffff 81 16 80f0 9fff ffff ffff ffff 83 00 00ff fe62 a2ff ffff ffff 81 03 e6e9 d74d 75d7 5d75 d75a f8f9 74eb d7af 5ebd 7af5 ebf0 f8f8 f979 7979 7979 7979 79fd 5f5f c7e3 f1f8 fc7e 3f1f 8fc7 e5fa ff6f d5f6 7d9f 67d9 f67d 9f67 d9f6 7edf abec f87c 3e1f 0f87 c3e1 f0f8 fd9f 1f1f 2f2f 2f2f 2f2f 2f2f 2f1f 2ebd 7af5 ebd7 ae9d 74e9 a56d 6b5a d6b5 a2b0 d249 24a5 ce36 db6d b6db 6db7 c6fd fd3d 3d3d 3d3d 3d3d 3d3b 7a7b fbfb fbfb fbfb fbfb fcfd bdfe dfb7 edfb 7eef bbee fbbe dfbb dbe7 f6fd ff7f dff7 fdff 7fdf f7fd feff 3fbb effb feff bfef fbfe ffbf efff ffff ffff ffff 83 00 00ff fe62 a2ff ffff ffff 81 03 e6fd bfab f9bf 57d5 f2eb 18f4 f9fd ffb7 f5ff 3feb fafc 7431 e9f4 fbff 77eb fd3f b3ec f2d5 efeb f6fe 1fbb f67e afdb f0f3 aaed edf7 fe3f 57ed fd7f bbe3 d2d3 dfe7 f87e 5f57 eefd 9fbb e5d6 2fdf e7f8 7eff abf7 7ecf ddf2 eb17 eff3 fc3f 7fd5 fbbf 67ee f975 8bf7 f9fe 1fbf eafd dfb3 f77c bac5 fbfc ff0f dff5 7eef d9fb be5d 62fd fe7f 87ef fabf 77ec fddf 2eb1 7eff 3fc3 f7fd 5fbb f67e ef97 58bf 7f9f e1fb feaf ddfb 3f77 cbac 5fbf cff0 fdff 57ee fd9f bbe5 d62f dfe7 f87e ffaf f77e cfab e5d6 2fe9 f3fc 7f7f d9f5 7edf abc7 431e 9f4f c7f8 7fff ffff ffff ffff 84 00 00ff dfb7 c5ff df0d 7fff ffff ffff 82 02 9afc 3eff b7e9 ede9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 dbef fbbe 9efe 9dbb 76ed dbb7 6edd bb76 eddb b76e ddb7 fbbe df9f af6d b6db 6db6 db6d b6db 6db6 db6d aff6 fd3d bbed 7bde f7bd ef7b def7 bdef 75f4 f7f4 dee9 2492 4924 924c fa7b 77da 6991 f4f7 efb4 d323 e9ed df69 a647 d3db bed3 4c8f a7b7 7da6 991f 4f7e fb4d 323e 9edd f69a 647d 3dbb ed34 c8fa 7b77 da69 647c fd7b 6100 0000 0045 bdfd 37bb 8888 8888 8888 8888 8aff ffff ffff ffff 84 00 00ff c9a7 1fff ffff ffff 82 0f 00ff 7704 4fff ffff ffff 84 00 00ff c9a7 1fff ffff ffff 82 0f 00ff 7704 bfff ffff ffff 84 00 00ff c9a7 1fff ffff ffff 82 13 80ff 7703 5fff ffff ffff 82 00 00ff 7743 1fff ffff ffff 82 00 00ff 7743 1fff ffff ffff 82 00 00ff 7745 efff ffff ffff 84 00 00ff df0c daff note 1 this table shows adv611/adv612 compressed data for one field in a color ramp video sequence. the sof# and sob# codes in the dat a are in bold text. bit error tolerance bit error tolerance is ensured because a bit error within a huffman coded stream does not cause #delimiter symbols to be misread by the adv611/adv612 in decode mode. the worst error that can occur is loss of a complete block of huffman data. with the adv611/adv612, this type of error results only in some blurring of the decoded image, not complete loss of the image.
adv611/adv612 C30C rev. 0 applying the adv611/adv612 this section includes the following topics: ? using the adv611/adv612 in computer applications ? using the adv611/adv612 in stand-alone applications ? configuring the host interface for 16- or 32-bit data paths ? connecting the video interface to popular video encoders and decoders ? getting the most out of the adv611/adv612 the following analog devices products should be considered in adv611/adv612 designs: ? adv7175/adv7176digital yuv to analog composite video encoder ? ad722analog rgb to analog composite video encoder ? ad1843audio codec with embedded video synchronization ? adsp-21xxfamily of fixed-point digital signal processors ? ad8xxxfamily of video operational amplifiers using the adv611/adv612 in computer applications many key features of the adv611/adv612 were driven by the demand ing cost and performance requirements of computer appl ications. the following adv611/adv612 features provide key advanta ges in computer applications, such as the one in figure 15. ? host interface the 512 double word fifo provides necessary buffering of compressed digital video to deal with pci bus latency. ? low cost external dram unlike many other real-time compression solutions, the adv611/adv612 does not require expensive external sram transform buffers or vram frame stores. a2 a3 d0Cd7 d8Cd15 d16Cd23 d24Cd31 a28 a29 a30 a31 host bus rd wr decode 1 decode 2 vclk vdata [0C7] llc xtal saa7111 27mhz pal or ntsc adr0 adr1 dq0Cdq7 dq8Cdq15 dq16Cdq23 dq24Cdq31 cs stats r lcode 24.576mhz xtal a0Ca8 d0Cd15 a0Ca8 dq1Cdq16 note: decode 1 asserts cs ~ on the adv611/adv612 for host addresses 0x4000,0000 through 0x4000,0013 decode 2 is host-specific adv611/adv612 dram (256k 3 16-bit) composite video input vclko toshiba tc514265dj/dz/dft-60 nec m pd424210ale-60 nec m pd42s4210ale-60 hitachi hm514265cj-60 any dram used with the adv611/adv612 must meet the minimum specifications outlined for the hyper mode drams listed fifo srq fifo stp fifo err y[0C7] be0ebe1 be2ebe3 rd wr hirq ras cas we ras cas oe wel weh ack figure 15. a suggested pc application design
adv611/adv612 C31C rev. 0 (mode 0 & slave mode) (ccir-656 mode) xtal 10k v 150 v vclk xtal adv611/adv612 vclko clock p7Cp0 adv7175 blank alsb vdata (7:0) figure 18. adv611/adv612 and adv7175 example interfacing block diagram using the raytheon tmc22153 video decoder raytheon has a whole family of video parts. any member of the family can be used. the user must select the part needed based on the requirements of the application. because the raytheon part does not include the a/ds, an external a/d is necessary in this design (or a pair of a/ds for s video). the part can be used in ccir-656 (d1) mode for a zero con- trol signal interface. special attention must be paid to the video output modes in order to get the right data to the right pins (see the following diagram). note that the circuit in figure 19 has not been built or tested. mode set to: cdec = 1 yuvt = 1 f422 = x tmc22153 y(2:9) clock xtal vclk vclk vdata (0:7) adv611/adv612 (ccir-656 & slave mode) figure 19. adv611/adv612 and tmc22153 example ccir-656 mode interface fl0 fl1 adr0 adr1 d8Cd23 d0Cd15 d16Cd31 pf4 fl2 cs rd rd lcode irq2 irql1 hirq a0Ca8 d0Cd15 a0Ca8 dq1Cdq16 the adsp-2185 internal clock rate double the input clock *the input clock rate = 1/2 of the internal clock rate, ranging from 12 to 21mhz adv611/adv612 adsp-2185 dram (256k 3 16-bit) toshiba tc514265dj/dz/dft-60 nec m pd424210ale-60 nec m pd42s4210ale-60 hitachi hm514265cj-60 any dram used with the adv611/adv612 must meet the minimum specifications outlined for the hyper mode drams listed wr wr pf5 be2 C be3 ras cas we ras cas oe wel weh vclk vdata [0C7] llc xtal saa7111 composite video input y[0C7] be0 C be1 27mhz pal or ntsc 24.576mhz xtal figure 16. alternate stand-alone application design using the adv611/adv612 in stand-alone applications figure 16 shows the adv611/adv612 in a noncomputer based applications. here, an adsp-2185 digital signal proces- sor provides host control and bw calculation services. note that all control and bw operations occur over the host interface in this design. connecting the adv611/adv612 to popular video decoders and encoders the following circuits are recommendations only. analog devices has not actually built or tested these circuits. using the philips saa7111 video decoder the saa7111 example circuit, which appears in figure 17, is used in this configuration on the adv611 cctvpipe demon- stration board. xtal (ccir-656 mode) saa7111 y(0:7) llc xtal vclk vdata (0:7) adv611/adv612 figure 17. adv611/adv612 and saa7111 example interfacing block diagram using the analog devices adv7175 video encoder because the adv7175 has a ccir-656 interface, it connects directly with the adv611/adv612 without glue logic. note that the adv7175 can only be used at ccir-601 sampling rates. the adv7175 example circuit, which appears in figure 18, is used in this configuration on the adv611 cctvpipe demon- stration board.
adv611/adv612 C32C rev. 0 harris 8115 clk2 27mhz pixel clock gsc vclk vdata (0C7) adv611/adv612 clk2 p8Cp15 8 figure 20. using the harris 8115 decoder getting the most out of adv611/adv612 how much compression can be expected the adv611/adv612 can be used in applications where up to 7500:1 compression is required. to express this in more meaningful terms, a digitized ntsc video signal at 167 mbit/s per second can be reduced to less than 25 kbits per second. to achieve this performance, the following approach could be used: 1. image compressed to 250:1 2. frame rate reduced to 1 frame per second (not uncommon in cctv applications) 3. quality box size less than 1% of the total image size 4. background contrast attenuated by 18 db the scenario described above used by analog devices on the cctvpipe evaluation board as the splash-screen after power- up. video quality is subjective, and therefore, it is highly recom- mended to perform a direct evaluation of the cctvpipe or the adv601 software codec to confirm that the compression per- formance is appropriate for a given application. while the adv611/adv612 can be used in very high compres- sion applications as outlined above, it is equally suitable for full resolution, 60 field per second visually loss-less applications. evaluation board there is a low cost stand-alone evaluation board for the adv611 called the cctvpipe (see block diagram). the cctvpipe provides a fast, simple, and low cost means of evaluating the performance of the adv611/adv612 and it is very similar to the evaluation board for the adv601lc, the videopipe. the cctvpipe is shipped with a small mouse to allow real-time quality box control. the board is also shipped with a small speaker to provide an audio alert signal when motion is detected in the video image. all of the source code and schematics for the cctvpipe are available from the analog devices web site free of charge (www.analog.com/wavelet). the exact part number is adv611- cctvpipe and it can be purchased through any analog devices authorized sales channel. a pci card is available for the adv601 called the videolab, which is bitstream compatible with the adv611/adv612. see the analog devices web site for further details. software codec analog devices has created two types of software products for cases where encoding or decoding in software are desirable. ? bit exact codec C nonreal-time bit exact encoder for windows ? 95 or 98. ? mmx/directshow player C real-time playback for windows 98 (pc monitor can be used to view the video directlyCno need for a dedicated tv monitor). field rate reduction as demonstrated by the cctvpipe evaluation board, field rates can be reduced to increase compression. the adv611/ adv612 allow this to be done in hardware (see register descriptions). edge enhancement and detection since the adv611/adv612 filters the image into wavelet subbands, edge information is isolated in the high pass blocks of image data (see the mallat diagram of the analog devices build- ing in the adv601lc data sheet for an illustration). by zeroing the low pass blocks, the adv611/adv612 will preserve only the high pass content of the image and thus enhance the edges in the image. the cctvpipe has a mode that demonstrates this feature. furthermore, these blocks can be huffman de- coded and analyzed for edge detection purposes. motion detection there are two known means of implementing motion detection with the adv611/adv612. 1. compare the image statistics between fields of video. this is the technique used on the cctvpipe for the motion detec- tion demo. 2. decode the smallest mallat block (block 39) and compare one field to the next. since these block are small (approximately 2400 pixels) the computational burden is much less than it would be for the entire image. for comparative purposes, the data samples in block 39 contain only 1/1024th of the total samples, or 1/512th the luminance samples. please contact analog device, inc. for information on how to implement this technique with quality box placement. serial port (sport) jp17 dram adsp-2185 h/w reset ez-ice jp16 rs-232 p1 adv611 h/w reset adv7175 dram adv611 h/w reset saa7111 y/c j2 cvbs j11 sram rom sram pals reset freeze up down select push buttons ccir-656 j12 +5vdc j10 adv611 cctvpipe y/c j8 cvbs j7 ccir-656 j13 figure 21. adv611 cctvpipe block diagram windows is a registered trademark of microsoft corporation.
C33C rev. 0 adv611/adv612 the adv611/adv612 video codec uses a bi-orthogonal (7, 9) wavelet transform. recommended operating conditions parameter description min max unit v dd supply voltage 4.50 5.50 v t amb ambient operating temperature 0 +70 c electrical characteristics parameter description test conditions min max unit v ih hi-level input voltage @ v dd = max 2.0 n/a v v il lo-level input voltage @ v dd = min n/a 0.8 v v oh hi-level output voltage @ v dd = min, i oh = C0.5 ma 2.4 n/a v v ol lo-level output voltage @ v dd = min, i ol = 2 ma n/a 0.4 v i ih hi-level input current @ v dd = max, v in = v dd max n/a 10 m a i il lo-level input current @ v dd = max, v in = 0 v n/a 10 m a i ozh three-state leakage current @ v dd = max, v in = v dd max n/a 10 m a i ozl three-state leakage current @ v dd = max, v in = 0 v n/a 10 m a c i input pin capacitance @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c n/a 8* pf c o output pin capacitance @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c n/a 8* pf *guaranteed but not tested. absolute maximum ratings* parameter description min max unit v dd supply voltage C0.3 +7 v v in input voltage n/a v dd 0.3 v v out output voltage n/a v dd 0.3 v t amb (adv611) am bient operating temperature 0 +70 c t amb (adv612) am bient operating temperature C25 +85 c t s storage temperature C65 +150 c t l lead temperature (5 sec) pqfp n/a +280 c *stresses greater than those listed above under absolute maximum ratings may cause permanent damage to the device. this is a st ress rating only; functional opera- tion of the device at these or any other conditions above those indicated in the pin definitions section of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. supply current and power parameter description test conditions min max unit i dd supply current (dynamic) @ v dd = max, t vclk _ cyc = 37 ns (at 27 mhz vclk) 0.11 0.27 a i dd supply current (soft reset) @ v dd = max, t vclk _ cyc = 37 ns (at 27 mhz vclk) 0.08 0.17 a i dd supply current (idle) @ v dd = max, t vclk _ cyc = none 0.01 0.02 a environmental conditions parameter description adv611/adv612 max unit q ca case-to-ambient thermal resistance 30 c/w q ja junction-to-ambient thermal resistance 35 c/w q jc junction-to-case thermal resistance 5 c/w specifications caution the adv611/adv612 is an esd (electrostatic discharge) sensitive device. electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. permanent damage may occur to devices subj ected to high energy electrostatic discharges. proper esd precautions are strongly recommended to avoid functional damage or performance degradation. the adv611/adv612 latchup immunity has been demonstrated at 3 200 ma/C200 ma on all pins when tested to industry standard/jedec methods. warning! esd sensitive device
adv611/adv612 C34C rev. 0 timing parameters this section contains signal timing information for the adv611/adv612. timing descriptions for the following items appear in th is section: ? clock signal timing ? video data transfer timing (ccir-656, and multiplexed philips formats) ? host data transfer timing (direct register read/write access) clock signal timing the diagram in this section shows timing for vclk input and vclko output. all output values assume a maximum pin loading of 50 pf. table xvii. video clock period, frequency, drift and jitter min vclk_cyc nominal vclk_cyc max vclk_cyc video format period period (frequency) period 1, 2 ccir-601 pal 35.2 ns 37 ns (27 mhz) 38.9 ns ccir-601 ntsc 35.2 ns 37 ns (27 mhz) 38.9 ns notes 1 vclk period drift = 0.1 (vclk_cyc/field. 2 vclk edge-to-edge jitter = 1 ns. table xviii. video clock duty cycle min nominal max vclk duty cycle 1 (40%) (50%) (60%) note 1 vclk duty cycle = t vclk_hi /(t vclk_lo ) 100. table xix. video clock timing parameters parameter description min max unit t vclk_cyc vclk signal, cycle time (1/frequency) at 27 mhz (see video clock period table) t vclko_d0 vclko signal, delay (when vclk2 = 0) at 27 mhz 10 29 ns t vclko_d1 vclko signal, delay (when vclk2 = 1) at 27 mhz 10 29 ns test conditions figure 22 shows test condition voltage reference and device loading information. these test conditions consider an output as disabled when the output stops driving and goes from the measured high or low voltage to a high impedance state. tests measure output disable time (t disable ) as the time between the reference input signal crossing +1.5 v and the time that the output reaches the high impedance state (also +1.5 v). simi- larly, these tests conditions consider an output as enabled when the output leaves the high impedance state and begins driving a measured high or low voltage. tests measure output enable time (t enable ) as the time between the reference input signal crossing +1.5 v and the time that the output reaches the measured high or low voltage. input reference signal output signal t disabled t enabled 1.5v v oh v ol v ih v il 1.5v input & output voltage/timing references device loading for ac measurements to output pin 2pf +1.5v i ol i oh figure 22. test condition voltage reference and device loading
adv611/adv612 C35C rev. 0 ccir-656 video format timing the diagrams in this section show transfer timing for pixel (ycrcb), line (horizontal), and frame (vertical) data in ccir-656 v ideo mode. all output values assume a maximum pin loading of 50 pf. note that in timing diagrams for ccir-656 video, the label ctrl indicates the vsync, hsync, and field pins. table xx. ccir-656 videodecode pixel (ycrcb) timing parameters parameter description min max units t vdata_dc_d vdata signals, decode ccir-656 mode, delay n/a 14 ns t vdata_dc_oh vdata signals, decode ccir-656 mode, output hold 4 n/a ns t ctrl_dc_d ctrl signals, decode ccir-656 mode, delay n/a 11 ns t ctrl_dc_oh ctrl signals, decode ccir-656 mode, output hold 5 n/a ns (o) ctrl (o) vclko t ctrl dc oh (o) vdata t vdata dc oh valid valid valid valid valid valid t ctrl dc d t vdata dc d figure 24. ccir-656 videodecode pixel (ycrcb) transfer timing table xxi. ccir-656 videoencode pixel (ycrcb) timing parameters parameter description min max units t vdata_ec_s vdata bus, encode ccir-656 mode, setup 2 n/a ns t vdata_ec_h vdata bus, encode ccir-656 mode, hold 5 n/a ns t ctrl_ec_d ctrl signals, encode ccir-656 mode, delay n/a 33 ns t ctrl_ec_oh ctrl signals, encode ccir-656 mode, output hold 20 n/a ns t vdata ec h (o) ctrl (i) vclk (i) vdata asserted valid asserted valid t ctrl ec oh t ctrl ec d t vdata ec s figure 25. ccir-656 videoencode pixel (ycrcb) transfer timing (i) vclk (o) vclko (vclk2 = 0) (i) vclko (vclk2 = 1) t vclk cyc t vclko d0 t vclko d1 note: use vclk for clocking video-encode operations and use vclko for clocking video-decode operations. do not try to use either clock for both encode and decode. figure 23. video clock timing
adv611/adv612 C36C rev. 0 figure 26. ccir-656 videoline (horizontal) and frame (vertical) transfer timing note that for ccir-656 videodecode and master line (horizontal) timing, vdata is synchronous with vclko. (o) stats_r (encode) (o) hsync (o) vsync (o) field 625 (pal) line # 621 622 623 624 625 1 2 3 4 5 6 310 311 312 313 314 315 316 317 318 319 21 22 23 24 309 encode / decode & master ccir-656 -- 625 (pal) f rame (vertical) transfer timing 334 335 336 337 (note: stats r is always lo for 45 cycles before going hi again. stats r is lo coming out of soft reset and goes high right after the adv611/adv612 finishes taking in the very first field.) (o) hsync (i) vclk (i) vdata ff xx ff xx sample 0 ntsc ccir-601 pixel, n = 720 (o) vclko (vclk2 = 0) (o) vclko (vclk2 = 1) encode ccir-656 -- line (horizontal) transfer timing (for decode vdata is synchronous to vclko) t vdata ec h t vdata ec s y 2 pal ccir-601 pixel, n = 720 cr 0 y 1 y 0 cb 2 cb 0 y n-2 cb n-2 cr n-2 y n-1 eav sav (o) stats r (encode) (o) hsync (o) vsync (o) field 525 (ntsc) line # 524 525 123456789 263264265266267268 282 283 284 262 335 336 337 338 encode / decode ccir-656 -- 525 (ntsc) f rame (vertical) transfer timing (note: stats r is always lo for 45 cycles before going hi again. stats r is lo coming out of soft reset and goes high right after the adv611/adv612 finishes taking in the very first field.) 20 21 22 23
adv611/adv612 C37C rev. 0 multiplexed philips video timing the diagrams in this section show transfer timing for pixel (ycrcb) data in multiplexed philips video mode. for line (horizonta l) and frame (vertical) data transfer timing, see figure 29. all output values assume a maximum pin loading of 50 pf. note that in timing diagrams for multiplexed philips video, the label ctrl indicates the vsync, hsync and field pins. table xxii. multiplexed philips videodecode and master pixel (ycrcb) timing parameters parameter description min max unit t vdata_dmm_d vdata bus, decode master multiplexed philips, delay n/a 14 ns t vdata_dmm_oh vdata bus, decode master multiplexed philips, output hold 4 n/a ns t ctrl_dmm_d ctrl signals, decode master multiplexed philips, delay n/a 11 ns t ctrl_dmm_oh ctrl signals, decode master multiplexed philips, output hold 5 n/a ns (o) ctrl (o) vclko t ctrl dmm oh (o) vdata t vdata dmm oh valid valid valid valid valid valid t vdata dmm d t ctrl dmm d figure 27. multiplexed philips videodecode and master pixel (ycrcb) transfer timing table xxiii. multiplexed philips videodecode and slave pixel (ycrcb) timing parameters parameter description min max unit t vdata_dsm_d vdata bus, decode slave multiplexed philips, delay n/a 14 ns t vdata_dsm_oh vdata bus, decode slave multiplexed philips, output hold 4 n/a ns t ctrl_dsm_s ctrl signals, decode slave multiplexed philips, setup 16 n/a ns t ctrl_dsm_h ctrl signals, decode slave multiplexed philips, hold 42 n/a ns (i) ctrl (o) vclko (o) vdata t ctrl dsm h valid valid valid valid t ctrl dsm s t vdata dsm oh t vdata dsm d figure 28. multiplexed philips videodecode and slave pixel (ycrcb) transfer timing
adv611/adv612 C38C rev. 0 figure 29. multiplexed philips videoCline (horizontal) and frame (vertical) transfer timing stats _ r (encode) hsync vsync 625 (pal) line # 621 622 623 624 625 1 2 3 4 5 6 310 311 312 313 314 315 316 317 318 319 8 23 24 309 7 320 321 (note: stats_r is always lo for 45 cycles before going hi again. stats r is lo coming out of soft reset and goes high right after the adv611/adv612 finishes taking in the very first field.) encode / decode & master multiplexed p hilips -- 625 (pal) frame (vertical) transfer timing 335 336 (note: adv611/adv612 gets hsynch from philips href) (o) field stats_r (encode) hsync vsync 525 (ntsc) line # 524 525 1 2 3 4 5 6 7 8 9 263 264 265 266 267 268 262 335 336 337 338 encode / decode & master multiplexed p hilips -- 525 (ntsc) f rame (vertical) transfer timing 282 283 284 22 23 24 21 (note: stats_r is always lo for 45 cycles before going hi again. stats r is lo coming out of soft reset and goes high right after the adv611/adv612 finishes taking in the very first field.) (o) field (note: adv611/adv612 in slave mode gets hsynch from philips href) (o) hsync (i) vclk (i) vdata sample 0 ntsc ccir-601 pixel, n = 720 (o) vclko (vclk2 = 0) (o) vclko (vclk2 = 1) t vdata_ec_h t vdata_ec_s y 2 pal ccir-601 pixel, n = 720 cr 0 y 1 y 0 cb 2 cb 0 y n-2 cb n-2 cr n-2 y n-1 encode master multiplexed philips -- line (horizontal) transfer timing (for decode vdata is synchronous to vclko)
adv611/adv612 C39C rev. 0 table xxiv. multiplexed philips videoencode and master pixel (ycrcb) timing parameters parameter description min max unit t vdata_emm_s vdata bus, encode master multiplexed philips, setup 2 n/a ns t vdata_emm_h vdata bus, encode master multiplexed philips, hold 5 n/a ns t ctrl_emm_d ctrl signals, encode master multiplexed philips, delay n/a 33 ns t ctrl_emm_oh ctrl signals, encode master multiplexed philips, output hold 20 n/a ns (o) ctrl (i) vclk (i) vdata asserted valid asserted valid t vdata emm h t ctrl emm oh t ctrl emm d t vdata emm s figure 30. multiplexed philips videoencode and master pixel (ycrcb) transfer timing table xxv. multiplexed philips videoencode and slave pixel (ycrcb) timing parameters parameter description min max unit t vdata_esm_s vdata bus, encode slave multiplexed philips mode, setup 2 n/a ns t vdata_esm_h vdata bus, encode slave multiplexed philips mode, hold 5 n/a ns t ctrl_esm_s ctrl signals, encode slave multiplexed philips mode, setup 5 n/a ns t ctrl_esm_h ctrl signals, encode slave multiplexed philips mode, hold 5 n/a ns (i) ctrl (i) vclk (i) vdata t ctrl esm h asserted t vdata esm h valid asserted valid t vdata esm s t ctrl esm s figure 31. multiplexed philips videoencode and slave pixel (ycrcb) transfer timing
adv611/adv612 C40C rev. 0 host interface (indirect address, indirect register data and interrupt mask/status) register timing the diagrams in this section show transfer timing for host read and write accesses to all of the adv611/adv612s direct registe rs, except the compressed data register. accesses to the indirect address, indirect register data, and interrupt mask/status regist ers are slower than access timing for the compressed data register. for information on access timing for the compressed data direct register, see the host interface (compressed data) register timing section. note that for accesses to the indirect address, ind irect register data and interrupt mask/status registers, your system must observe ack and rd or wr assertion timing. table xxvi. host (indirect address, indirect data, and interrupt mask/status) read timing parameters parameter description min max unit t rd_d_rdc rd signal, direct register, read cycle time (at 27 mhz vclk) n/a 1 n/a ns t rd_d_pwa rd signal, direct register, pulsewidth asserted (at 27 mhz vclk) n/a 1 n/a ns t rd_d_pwd rd signal, direct register, pulsewidth deasserted (at 27 mhz vclk) 5 n/a ns t adr_d_rds adr bus, direct register, read setup 2 n/a ns t adr_d_rdh adr bus, direct register, read hold 2 n/a ns t data_d_rdd data bus, direct register, read delay n/a 171.6 2, 3 ns t data_d_rdoh data bus, direct register, read output hold (at 27 mhz vclk) 26 n/a ns t rd_d_wrt wr signal, direct register, read-to-write turnaround (at 27 mhz vclk) 48.7 4 n/a ns t ack_d_rdd ack signal, direct register, read delayed (at 27 mhz vclk) 8.6 287.1 5, 6 ns t ack_d_rdoh ack signal, direct register, read output hold (at 27 mhz vclk) 11 n/a ns notes 1 rd input must be asserted (low) until ack is asserted (low). 2 maximum t data_d_rdd varies with vclk according to the formula: t data_d_rdd (max) = 4 (vclk period) +16. 3 during stats_r deasserted (low) conditions, t data_d_rdd may be as long as 52 vclk periods. 4 minimum t rd_d_wrt varies with vclk according to the formula: t rd_d_wrt (min) = 1.5 (vclk period) C4.1. 5 maximum t ack_d_rdd varies with vclk according to formula: t ack_d_rdd (max) = 7 (vclk period) +14.8. 6 during stats_r deasserted (low) conditions, t ack_d_rdd may be as long as 52 vclk periods. valid valid valid valid (i) adr, be , cs (i) rd (o) data (o) ack (i) wr t adr d rds t ack d rdoh t rd d rdc t rd d pwa t rd d pwd t adr d rdh t data d rdd t data d rdoh t rd d wrt t ack d rdd figure 32. host (indirect address, indirect register data, and interrupt mask/status) read transfer timing
adv611/adv612 C41C rev. 0 table xxvii. host (indirect address, indirect data and interrupt mask/status) write timing parameters parameter description min max unit t wr_d_wrc wr signal, direct register, write cycle time (at 27 mhz vclk) n/a 1 n/a ns t wr_d_pwa wr signal, direct register, pulsewidth asserted (at 27 mhz vclk) n/a 1 n/a ns t wr_d_pwd wr signal, direct register, pulsewidth deasserted (at 27 mhz vclk) 5 n/a ns t adr_d_wrs adr bus, direct register, write setup 2 n/a ns t adr_d_wrh adr bus, direct register, write hold 2 n/a ns t data_d_wrs data bus, direct register, write setup C10 n/a ns t data_d_wrh data bus, direct register, write hold 0 n/a ns t wr_d_rdt wr signal, direct register, read turnaround (after a write) (at 27 mhz vclk) 35.6 2 n/a ns t ack_d_wrd ack signal, direct register, write delay (at 27 mhz vclk) 8.6 182.1 3, 4 ns t ack_d_wroh ack signal, direct register, write output hold 11 n/a ns notes 1 wr input must be asserted (low) until ack is asserted (low). 2 minimum t wr_d_rdt varies with vclk according to the formula: t wr_d_rdt (min) = 0.8 (vclk period) +7.4. 3 maximum t wr_d_wrd varies with vclk according to the formula: t ack_d_wrd (max) = 4.3 (vclk period) +14.8. 4 during stats_r deasserted (low) conditions, t ack_d_wrd may be as long as 52 vclk periods. valid valid valid valid (i) adr, be , cs (i) wr (i) data (o) ack (i) rd t adr d wrs t data d wrs t wr d wrc t wr d pwa t wr d pwd t adr d wrh t data d wrh t ack d wrd t wr d rdt t ack d wroh figure 33. host (indirect address, indirect register data, and interrupt mask/status) write transfer timing
adv611/adv612 C42C rev. 0 host interface (compressed data) register timing the diagrams in this section show transfer timing for host read and write transfers to the adv611/adv612s compressed data register. accesses to the compressed data register are faster than access timing for the indirect address, indirect register da ta, and interrupt mask/status registers. for information on access timing for the other registers, see the host interface (indirect add ress , indirect register data, and interrupt mask/status) register timing section. also note that as long as your system observes the rd or wr signal assertion timing, your system does not have to wait for the ack signal between new compressed data addresses. table xxviii. host (compressed data) read timing parameters parameter description min max unit t rd_cd_rdc rd signal, compressed data direct register, read cycle time 28 n/a ns t rd_cd_pwa rd signal, compressed data direct register, pulsewidth asserted 10 n/a ns t rd_cd_pwd rd signal, compressed data direct register, pulsewidth deasserted 10 n/a ns t adr_cd_rds adr bus, compressed data direct register, read setup 2 n/a ns t adr_cd_rdh adr bus, compressed data direct register, read hold (at 27 mhz vclk) 2 n/a ns t data_cd_rdd data bus, compressed data direct register, read delay n/a 10 ns t data_cd_rdoh data bus, compressed data direct register, read output hold 18 n/a ns t ack_cd_rdd ack signal, compressed data direct register, read delay n/a 18 ns t ack_cd_rdoh ack signal, compressed data direct register, read output hold 9 n/a ns (i) adr, be , cs (i) rd (o) data (o) ack valid valid valid valid t adr cd rds t data cd rdd t ack cd rdd t ack cd rdoh t data cd rdoh t adr cd rdh t rd cd rdc t rd cd pwa t rd cd pwd figure 34. host (compressed data) read transfer timing
adv611/adv612 C43C rev. 0 table xxix. host (compressed data) write timing parameters parameter description min max unit t wr_cd_wrc wr signal, compressed data direct register, write cycle time 28 n/a ns t wr_cd_pwa wr signal, compressed data direct register, pulsewidth asserted 10 n/a ns t wr_cd_pwd wr signal, compressed data direct register, pulsewidth deasserted 10 n/a ns t adr_cd_wrs adr bus, compressed data direct register, write setup 2 n/a ns t adr_cd_wrh adr bus, compressed data direct register, write hold 2 n/a ns t data_cd_wrs data bus, compressed data direct register, write setup 2 n/a ns t data_cd_wrh data bus, compressed data direct register, write hold 2 n/a ns t ack_cd_wrd ack signal, compressed data direct register, write delay n/a 19 ns t ack_cd_wroh ack signal, compressed data direct register, write output hold 9 n/a ns (i) adr, be , cs (i) wr (i) data (o) ack valid t adr cd wrh t adr cd wrs t data cd wrs t data cd wrh t ack cd wrd t wr cd wrc t ack cd wroh valid valid valid t wr cd pwa t wr cd pwd figure 35. host (compressed data) write transfer timing
adv611/adv612 C44C rev. 0 pin pin pin name type 81 vdata4 i/o 82 gnd ground 83 vdd power 84 vdata3 i/o 85 vdata2 i/o 86 vdata1 i/o 87 vdata0 i/o 88 nc* nc 89 nc* nc 90 gnd ground 91 data31 i/o 92 data30 i/o 93 data29 i/o 94 data28 i/o 95 data27 i/o 96 data26 i/o 97 data25 i/o 98 data24 i/o 99 data23 i/o 100 data22 i/o 101 data21 i/o 102 data20 i/o 103 vdd power 104 data19 i/o 105 data18 i/o 106 data17 i/o 107 data16 i/o 108 gnd ground 109 gnd ground 110 data15 i/o 111 data14 i/o 112 data13 i/o 113 data12 i/o 114 data11 i/o 115 data10 i/o 116 data9 i/o 117 data8 i/o 118 data7 i/o 119 data6 i/o 120 data5 i/o pin pin pin name type 41 cas o 42 we o 43 vdd power 44 vdd power 45 ddat15 i/o 46 ddat14 i/o 47 ddat13 i/o 48 ddat12 i/o 49 ddat11 i/o 50 ddat10 i/o 51 ddat9 i/o 52 ddat8 i/o 53 ddat7 i/o 54 ddat6 i/o 55 ddat5 i/o 56 ddat4 i/o 57 ddat3 i/o 58 ddat2 i/o 59 ddat1 i/o 60 ddat0 i/o 61 gnd ground 62 vdd power 63 gnd ground 64 vdd power 65 stall i 66 gnd ground 67 enc o 68 vclko o 69 vdd power 70 xtal i 71 vclk i 72 gnd ground 73 field i or o 74 hsync i or o 75 vsync i or o 76 gnd ground 77 vdd power 78 vdata7 i/o 79 vdata6 i/o 80 vdata5 i/o pin pin pin name type 1 data4 i/o 2 data3 i/o 3 data2 i/o 4 data1 i/o 5 data0 i/o 6 vdd power 7 gnd ground 8 rd i 9 wr i 10 cs i 11 adr1 i 12 adr0 i 13 gnd ground 14 be2 C be3 i 15 be0 C be1 i 16 gnd ground 17 reset i 18 vdd power 19 ack o 20 vdd power 21 gnd ground 22 hirq o 23 lcode o 24 fifo_srq o 25 stats_r o 26 vdd power 27 gnd ground 28 gnd ground 29 vdd power 30 dadr8 o 31 dadr7 o 32 dadr6 o 33 dadr5 o 34 dadr4 o 35 dadr3 o 36 dadr2 o 37 dadr1 o 38 dadr0 o 39 gnd ground 40 ras o adv611/adv612 lqfp pinouts *apply a 10 k w pull-down resistor to this pin.
adv611/adv612 C45C rev. 0 adv611/adv612 pin configuration 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 5 4 3 2 7 6 9 8 1 32 33 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 60 59 58 57 54 53 52 51 56 55 34 pin 1 identifier top view (not to scale) 86 87 89 84 85 82 83 81 90 80 88 75 76 77 78 73 74 72 70 71 79 69 67 68 65 66 63 64 61 62 112 113 114 115 116 117 118 119 12 0 111 103 110 109 108 107 106 104 102 101 100 99 98 97 96 95 94 93 92 91 105 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 gnd gnd data16 data17 data18 data19 vdd data2 0 data2 1 data2 2 data2 3 data2 4 data2 5 data2 6 data2 7 data2 8 data2 9 data3 0 data3 1 dadr7 dadr6 dadr5 dadr4 dadr3 dadr2 dadr1 dadr0 gnd ras cas we vdd vdd ddat15 ddat14 ddat13 ddat12 ddat11 ddat10 ddat9 ddat8 ddat7 ddat6 ddat5 ddat4 ddat3 ddat2 ddat1 ddat0 gnd nc* nc* vdata0 vdata1 vdata2 vdata3 vdd gnd vdata4 vdata5 vdata6 vdata7 vclko enc gnd stall vdd gnd vdd gnd vdd gnd vsync hsync field gnd vclk xtal vdd data4 data3 data2 data1 data0 vdd gnd rd wr cs adr1 adr0 gnd be2 C be3 be0 C be1 gnd reset vdd ack vdd gnd hirq lcode fifo srq stats r vdd gnd gnd vdd dadr8 *apply a 10k v pull down resistor to this pin adv611/adv612 lqfp
adv611/adv612 C46C rev. 0 120-lead lqfp (st-120) top view (pins down) 1 30 31 61 60 90 120 91 0.457 (11.6) bsc sq 0.638 (16.20) 0.630 (16.00) sq 0.622 (15.80) 0.559 (14.20) 0.551 (14.00) sq 0.543 (13.80) seating plane 0.063 (1.60) max coplanarity 0.003 (0.08) max 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) 0.016 (0.40) bsc * 7 8 3.5 8 0 8 0.008 (0.20) 0.004 (0.09) 0.009 (0.23) 0.007 (0.18) 0.005 (0.13) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) * the actual position of each lead is within 0.07 mm lateral to the pins true position. center figures are typical unless otherwise noted ordering guide part number ambient temperature range 1 package description package options 2 adv611jst 0 c to +70 c 120-lead lqfp st-120 adv612bst 3 C25 c to +85 c 120-lead lqfp st-120 notes 1 j = commercial temperature range (0 c to +70 c). 2 st = plastic thin quad flatpack. 3 b = standard industrial temperature range (C25 c to +85 c). outline dimensions dimensions shown in inches and (mm). c3399C3C1/99 printed in u.s.a.

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